Datasheet

LTC3441
5
3441fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
PMOS R
DS(ON)
Minimum Start Voltage
TEMPERATURE (°C)
–50
0.05
PMOS R
DS(ON)
(Ω)
0.07
0.09
0.11
–25
5
35 65
3441 G15
95
0.13
0.15
0.06
0.08
0.10
0.12
0.14
125
V
IN
= V
OUT
= 3.6V
SWITCHES A AND D
TEMPERATURE (°C)
–55
2.10
MINIMUM START VOLTAGE (V)
2.15
2.20
2.25
2.30
–25 5 35 65
3441 G16
95 125
UU
U
PI FU CTIO S
SHDN/SS (Pin 1): Combined Soft-Start and Shutdown.
Applied voltage < 0.4V shuts down the IC. Tie to >1.4V to
enable the IC and >2.4V to ensure the error amp is not
clamped from soft-start. An RC from the shutdown com-
mand signal to this pin will provide a soft-start function by
limiting the rise time of the V
C
pin.
GND (Pin 2): Signal Ground for the IC.
PGND (Pins 3, 6, 13 Exposed Pad): Power Ground for the
Internal NMOS Power Switches
SW1 (Pin 4): Switch pin where the internal switches A and
B are connected. Connect inductor from SW1 to SW2. An
optional Schottky diode can be connected from this SW1
to ground. Minimize trace length to keep EMI down.
SW2 (Pin 5): Switch pin where the internal switches C
and D are connected. An optional Schottky diode can be
connected from SW2 to V
OUT
(it is required where
V
OUT
> 4.3V). Minimize trace length to keep EMI down.
MODE/SYNC (Pin 7): Burst Mode Select and Oscillator
Synchronization.
MODE/SYNC = High: Enable Burst Mode Operation.
During the period where the IC is supplying energy to
the output, the inductor peak inductor current will reach
0.8A and return to zero current on each cycle. In Burst
Mode operation the operation is variable frequency,
which provides a significant efficiency improvement at
light loads. The Burst Mode operation will continue until
the pin is driven low.
MODE/SYNC = Low: Disable Burst Mode operation and
maintain low noise, constant frequency operation .
MODE/SYNC = External CLK : Synchronization of the
internal oscillator and Burst Mode operation disable. A
clock pulse width between 100ns and 2μs and a clock
frequency between 2.3MHz and 3.4MHz (twice the
desired frequency) is required to synchronize the IC.
f
OSC
= f
SYNC
/2
V
OUT
(Pin 8): Output of the Synchronous Rectifier. A filter
capacitor is placed from V
OUT
to GND. A ceramic bypass
capacitor is recommended as close to the V
OUT
and GND
pins as possible.
PV
IN
(Pin 9): Power V
IN
Supply Pin. A 10μF ceramic capaci-
tor is recommended as close to the PV
IN
and PGND pins
as possible
V
IN
(Pin 10): Input Supply Pin. Internal V
CC
for the IC.
V
C
(Pin 11): Error Amp Output. A frequency compensation
network is connected from this pin to the FB pin to
compensate the loop. See the section “Compensating the
Feedback Loop” for guidelines.
FB (Pin 12): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 2.4V to
5.25V. The feedback reference voltage is typically 1.22V.
NMOS R
DS(ON)
TEMPERATURE (°C)
–55
0.05
NMOS R
DS(ON)
(Ω)
0.07
0.09
0.11
0.13
0.15
–25
53565
3441 G14
95 125
V
IN
= V
OUT
= 3.6V
SWITCHES B AND C