Datasheet

LTC3429/LTC3429B
5
3429fa
UU
U
PI FU CTIO S
SW (Pin 1): Switch Pin. Connect inductor between SW
and V
IN
. Keep these PCB trace lengths as short and wide
as possible to reduce EMI and voltage overshoot. If the
inductor current falls to zero, or SHDN is low, an internal
150Ω antiringing switch is connected from SW to V
IN
to
minimize EMI.
GND (Pin 2): Signal and Power Ground. Provide a short
direct PCB path between GND and the (–) side of the output
capacitor(s).
FB (Pin 3): Feedback Input to the g
m
Error Amplifier.
Connect resistor divider tap to this pin. The output voltage
can be adjusted from 2.5V to 5V by:
V
OUT
= 1.23V • [1 + (R1/R2)]
SHDN (Pin 4): Logic Controlled Shutdown Input.
SHDN = High: Normal free running operation, 500kHz
typical operating frequency.
SHDN = Low: Shutdown, quiescent current <1µA.
Output capacitor can be completely discharged through
the load or feedback resistors. A 150Ω resistor is
internally connected between SW and V
IN
.
V
OUT
(Pin 5): Output Voltage Sense Input and Drain of the
Internal Synchronous Rectifier MOSFET. Bias is derived
from V
OUT
. PCB trace length from V
OUT
to the output filter
capacitor(s) should be as short and wide as possible. V
OUT
is completely disconnected from V
IN
when SHDN is low
due to the output disconnect feature.
V
IN
(Pin 6): Battery Input Voltage. The device gets its
start-up bias from V
IN
. Once V
OUT
exceeds V
IN
, bias
comes from V
OUT
. Thus, once started, operation is com-
pletely independent from V
IN
. Operation is only limited by
the output power level and the battery’s internal series
resistance.
1.23V
REF
Burst Mode
OPERATION
CONTROL
SHUTDOWN
CONTROL
SLOPE
COMP
PWM
CONTROL
START-UP
OSC
MUX
A
B
A/B
RAMP
GEN
500kHz
FB
3429 BD
3
V
OUT
V
IN
L1
5
SW
0.45Ω
WELL
SWITCH
1
V
IN
1V TO 4.4V
6
SHDN
4
GND
2
–
+
g
m
ERROR
AMP
–
+
V
OUT
GOOD
–
–
+
PWM
COMPARATOR
R
C
80k
SHUTDOWN
C
C
150pF
C
P2
2.5pF
R2
R1
SLEEP
Σ
SYNC
DRIVE
CONTROL
0.35Ω
2.3V
C
OUT
C
PL
(OPTIONAL)
2.5V TO 5V
C
IN
+
CURRENT
SENSE
BLOCK DIAGRA
W