Datasheet

4
LTC3426
3426fa
UU
U
PI FU CTIO S
SW (Pin 1): Switch Pin. Connect inductor between SW and
V
IN
. A Schottky diode is connected between SW and V
OUT
.
Keep these PCB trace lengths as short and wide as
possible to reduce EMI and voltage overshoot. If the
inductor current falls to zero, an internal 100Ω antiringing
switch is connected from SW to V
IN
to minimize EMI.
GND (Pin 2): Signal and Power Ground. Provide a short
direct PCB path between GND and the (–) side of the output
capacitor(s).
FB (Pin 3): Feedback Input to the g
m
Error Amplifier.
Connect resistor divider tap to this pin. The output voltage
can be adjusted from 2.5V to 5V by:
V
R
R
OUT
=+
⎛
⎝
⎜
⎞
⎠
⎟
122 1
1
2
.•
SHDN (Pin 4): Logic Controlled Shutdown Input.
SHDN = High: Normal free running operation
SHDN = Low: Shutdown, quiescent current < 1µA
Typically, SHDN should be connected to V
IN
through a 1M
pull-up resistor.
V
OUT
(Pin 5): Output Voltage Sense Input. The NMOS
switch gate drive is derived from the greater of V
OUT
and
V
IN
.
V
IN
(Pin 6): Input Supply. Must be locally bypassed.
BLOCK DIAGRA
W
Figure 1
4
SHUTDOWN AND
SOFT-START
1.22V
REFERENCE
RAMP
GENERATOR
1.2MHz
OSCILLATOR
3426 F01
PWM LOGIC
AND DRIVER
Σ
–
+
3
FB
FB
V
OUT
SHDN
SW
A1
–
+
–
+
A2
R
C
R2 (EXTERNAL)
R1 (EXTERNAL)
0.02Ω
C
C
1
GND
2
V
IN
6
V
OUT
COMPARATOR
5