Datasheet

LTC3422
13
3422fa
APPLICATIO S I FOR ATIO
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conduct heat away from the LTC3422 and into the copper
plane with as much area as possible. In the event that the
junction temperature gets too high, the peak current limit
will automatically be decreased. If the junction tempera-
ture continues to rise, the LTC3422 will go into thermal
shutdown and all switching will stop until the internal
temperature drops.
V
IN
> V
OUT
Operation
The LTC3422 will maintain voltage regulation when the
input voltage is above the output voltage. This is achieved
by terminating the switching of the synchronous P-chan-
nel MOSFET and applying V
IN
statically on the gate. This
will ensure the volt • seconds of the inductor will reverse
during the time current is flowing to the output. Since this
mode will dissipate more power in the LTC3422, the
maximum output current is limited in order to maintain an
acceptable junction temperature and is given by:
I
T
VV
OUT MAX
A
IN OUT
()
–
•( .)–
=
+
()
125
43 1 5
where T
A
= ambient temperature.
For example at V
IN
= 4.5V, V
OUT
= 3.3V and T
A
= 85°C, the
maximum output current is 345mA.
Short Circuit
The LTC3422 output disconnect feature allows output
short circuit while maintaining a maximum internally set
current limit. However, the LTC3422 also incorporates
internal features such as current limit foldback and ther-
mal shutdown for protection from an excessive overload
or short circuit. During a prolonged short circuit the
current limit folds back to 0.75A typical should V
OUT
drop
below approximately 666mV. This 0.75A current limit
remains in effect until V
OUT
exceeds approximately 800mV,
at which time the steady-state current limit is restored.
Closing the Feedback Loop
The LTC3422 utilizes current mode control with internal
adaptive slope compensation. Current mode control elimi-
nates the 2nd order filter due to the inductor and output
capacitor exhibited in voltage mode controllers, thus
simplifying it to a single pole filter response. The product
of ‘the modulator control to output DC gain’ and ‘the error
amp open-loop gain’ gives the DC gain of the system:
GG G
V
V
G
V
I
G
DC CONTROL OUTPUT EA
REF
OUT
CONTROL OUTPUT
IN
OUT
EA
=
= ≈
_
_
••
•
;
2
2000
The output filter pole is given by:
ƒ
FILTER POLE
OUT
OUT OUT
I
VC
_
••
=
π
where C
OUT
is the output filter capacitor.
The output filter zero is given by:
ƒ
FILTER ZERO
ESR OUT
RC
_
•• •
=
π
1
2
where R
ESR
is the capacitor equivalent series resistance.
A troublesome feature of the boost regulator topology is
the right-half plane zero (RHP), given by:
ƒ
RHPZ
IN
OUT OUT
V
ILV
=
π
2
2• • • •
At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.
The typical error amplifier compensation is shown in
Figure 3. The equations for the loop dynamics are as
follows:
ƒ
ƒ
ƒ
POLE
C
ZERO
ZC
POLE
ZC
eC
RC
RC
1
1
1
1
2
2
1
2206
1
2
1
2
≈
π
≈
π
≈
π
•• •
•• •
•• •
which is extremely close to DC