Datasheet

LTC3421
13
3421f
APPLICATIO S I FOR ATIO
WUUU
volts • seconds of the inductor will reverse during the time
current is flowing to the output. Since this mode will
dissipate more power in the IC, the maximum output
current is limited in order to maintain an acceptable
junction temperature.
I
T
VV
OUT MAX
A
IN OUT
()
–
•.–
=
+
()
()
125
40 1 5
where T
A
= ambient temperature.
For example at V
IN
= 4.5V and V
OUT
= 3.3V, the maximum
output current is 370mA.
Short Circuit
The LTC3421 output disconnect feature allows output short
circuit while maintaining a maximum set current limit. The
IC has incorporated internal features such as current limit
and thermal shutdown for protection from an excessive
overload or short circuit. In applications that require a pro-
longed short circuit, it is recommended to limit the power
dissipation in the IC to maintain an acceptable junction
temperature. The circuit in Figure 2 will limit the maximum
current during a prolonged short by reducing the current
limit value in a short circuit by disconnecting R2 with the
N-channel MOSFET switch. R3 and C1 provide a soft-start
function after a short circuit. Resistor R1 lowers the cur-
rent limit value as V
IN
rises, maintaining a relatively con-
stant power. The current limit equation for the circuit in
Figure 2 is given by:
I
R
V
R
LIMIT
LIM
IN
=






06 06
1
250
.
–
–.
•
where I
LIMIT
is in Amps; R
LIM
and R1 are in kΩ.
Closing the Feedback Loop
The LTC3421 uses current mode control with internal
adaptive slope compensation. Current mode control elimi-
nates the 2nd order filter due to the inductor and output
capacitor exhibited in voltage mode controllers, and sim-
plifies it to a single pole filter response. The product of the
modulator control to output DC gain and the error amp
open-loop gain gives the DC gain of the system:
GG
V
V
G
V
I
G
DC EA
REF
OUT
CONTROL
IN
OUT
EA
=
=≈
G
CONTROL_OUTPUT
••
•
,
2
2000
The output filter pole is given by:
f
I
VC
FILTER POLE
OUT
OUT OUT
_
••
=
π
where C
OUT
is the output filter capacitor.
The output filter zero is given by:
f
RC
FILTER ZERO
ESR OUT
_
•• •
=
π
1
2
where R
ESR
is the capacitor equivalent series resistance.
A troublesome feature of the boost regulator topology is
the right-half plane zero (RHP) and is given by:
f
V
IL
RHPZ
IN
OUT
=
π
2
2• • •
At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.
The typical error amp compensation is shown in Figure 3.
The equations for the loop dynamics are as follows:
f
eC
f
RC
f
RC
POLE
C
ZERO
ZC
POLE
ZC
1
1
1
1
2
2
1
2206
1
2
1
2
≈
π
≈
π
≈
π
•• •
•• •
•• •
which is extremely close to DC
Figure 2. Current Limit Foldback Circuit for
Extended Short Conditions
8
R2
50k
C1
0.1µF
3421 F02
R1
1M
R3
10k
R
LIM
100k
VN2222
I
LIM
TO V
IN
TO V
OUT