Datasheet

LTC3418
13
3418fb
load currents can be misleading since the actual power
lost is of no consequence.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the Electrical Charac-
teristics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate
is switched from high to low to high again, a packet
of charge dQ moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger
than the DC bi a s curr en t. In cont inuous mo de, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode the average output current fl owing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. Thus, to obtain I
2
R losses, simply add
R
SW
to R
L
and multiply the result by the square of the
average output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3418 does not dissipate much
heat due to its high ef ciency.
But, in applications where the LTC3418 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part.
If the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3418 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise
is given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature. For the 38-Lead 5mm × 7mm
QFN package, the θ
JA
is 34°C/W.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
N o t e t h a t a t h i g h e r s u p p l y v o l t a g e s , t h e j u n c t i o n t e m p e r a t u r e
is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current.
When a load step occurs, V
OUT
immediately shifts by an
amount equal to ΔI
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ΔI
LOAD
also begins to charge
or discharge C
OUT
generating a feedback error signal
used by the regulator to return V
OUT
to its steady-state
value. During this recovery time, V
OUT
can be monitored
for overshoot or ringing that would indicate a stability
problem. The I
TH
pin external components and output
capacitor shown in the Typical Application on the front
page of this data sheet will provide adequate compensa-
tion for most applications.
Design Example
As a design example, consider using the LTC3418 in an
application with the following specifi cations: V
IN
= 3.3V,
V
OUT
= 2.5V, I
OUT(MAX)
= 8A, I
OUT(MIN)
= 200mA, f = 1MHz.
APPLICATIONS INFORMATION