Datasheet

LTC3417
15
3417fd
APPLICATIONS INFORMATION
3) I
2
R losses are calculated from the DC resistances of the
internal switches, R
SW
, and the external inductor, R
L
. In
continuous mode, the average output current fl owing
through inductor L is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R
DS(ON)
and the duty cycle (DC) as
follows:
R
SW
= (R
DS(ON)
TOP)(DC) + (R
DS(ON)
BOT)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
(R
SW
+ R
L
)
where R
L
is the resistance of the inductor.
4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional effi ciency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C
IN
has adequate
charge storage and very low ESR
COUT
at the switching
frequency. Other losses including diode conduction
losses during dead-time and inductor core losses gener-
ally account for less than 2% total additional loss.
Thermal Considerations
The LTC3417 requires the package Exposed Pad (PGND2/
GNDD pin) to be well soldered to the PC board. This gives
the DFN and TSSOP packages exceptional thermal proper-
ties, compared to similar packages of this size, making it
diffi cult in normal operation to exceed the maximum junc-
tion temperature of the part. In a majority of applications,
the LTC3417 does not dissipate much heat due to its high
effi ciency. However, in applications where the LTC3417 is
running at high ambient temperature with low supply volt-
age and high duty cycles, such as in dropout, the heat dis-
sipated may exceed the maximum junction temperature of
the part. If the junction temperature reaches approximately
150°C, both switches in both regulators will be turned off
and the SW nodes will become high impedance.
To prevent the LTC3417 from exceeding its maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
RISE
= P
D
• θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
As an example, consider the case when the LTC3417 is
in dropout in both regulators at an input voltage of 3.3V
with load currents of 1.4A and 800mA. From the Typical
Performance Characteristics graph of Switch Resistance,
the R
DS(ON)
resistance of the 1.4A P-channel switch is
0.09 and the R
DS(ON)
of the 800mA P-channel switch
is 0.163. The power dissipated by the part is:
PD = I
1
2
• R
DS(ON)1
+ I
2
2
• R
DS(ON)2
PD = 1.4
2
• 0.09 + 0.8
2
• 0.163
PD = 281mW
The DFN package junction-to-ambient thermal resistance,
θ
JA
, is about 43°C/W. Therefore, the junction temperature
of the regulator operating in a 70°C ambient temperature
is approximately:
T
J
= 0.281 • 43 + 70
T
J
= 82.1°C
Remembering that the above junction temperature is
obtained from an R
DS(ON)
at 25°C, we might recalculate
the junction temperature based on a higher R
DS(ON)
since
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.