Datasheet

LTC3417A
15
3417afc
applicaTions inForMaTion
low to high to low again, a packet of charge moves from
V
IN
to ground. The resulting charge over the switching
period is a current out of V
IN
that is typically much larger
than the DC bias current. The gate charge losses are
proportional to V
IN
and thus their effects will be more
pronounced at higher supply voltages.
3) I
2
R losses are calculated from the DC resistances of the
internal switches, R
SW
, and the external inductor, R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R
DS(ON)
and the duty cycle (DC) as
follows:
R
SW
= (R
DS(ON)
TOP)(DC) + (R
DS(ON)
BOT)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
(R
SW
+ R
L
)
where R
L
is the resistance of the inductor.
4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design
of a system. The internal battery and fuse resistance
losses can be minimized by making sure that C
IN
has
adequate charge storage and very low ESR
COUT
at
the switching frequency. Other losses including diode
conduction losses during dead-time and inductor core
losses generally account for less than 2% total additional
loss.
Thermal Considerations
The LTC3417A requires the package Exposed Pad
(PGND2/GNDD pin) to be well soldered to the PC board.
This gives the DFN and TSSOP packages exceptional
thermal properties, compared to similar packages of this
size, making it difficult in normal operation to exceed the
maximum junction temperature of the part. In a majority
of applications, the LTC3417A does not dissipate much
heat due to its high efficiency. However, in applications
where the LTC3417A is running at high ambient tem-
perature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both switches
in both regulators will be turned off and the SW nodes will
become high impedance.
To prevent the LTC3417A from exceeding its maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
RISE
= P
D
• θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
As an example, consider the case when the LTC3417A is
in dropout in both regulators at an input voltage of 3.3V
with load currents of 1.5A and 1A. From the Typical Per-
formance Characteristics graph of Switch Resistance, the
R
DS(ON)
resistance of the 1.5A P-channel switch is 0.09Ω
and the R
DS(ON)
of the 1A P-channel switch is 0.163Ω.
The power dissipated by the part is:
PD = I
1
2
• R
DS(ON)1
+ I
2
2
• R
DS(ON)2
PD = 1.5
2
• 0.09 + 1
2
• 0.163
PD = 366mW
The DFN package junction-to-ambient thermal resistance,
θ
JA
, is about 43°C/W. Therefore, the junction temperature
of the regulator operating in a 70°C ambient temperature
is approximately:
T
J
= 0.366 • 43 + 70
T
J
= 85.7°C