Datasheet

LTC3415
7
3415fa
SGND (Pin 2): Signal Ground. Return ground path for
all analog and low power circuitry. Single connection to
PGND on system board.
PLLLPF (Pin 3): Phase-Locked-Loop Lowpass Filter. The
PLL’s lowpass fi lter is tied to this pin. In spread spectrum
mode, placing a capacitor here to SGND controls the slew
rate from one frequency to the next. Alternatively, fl oating
this pin allows normal running frequency at 1.5MHz, tying
this pin to SV
IN
forces the part to run at 1.33 times its normal
frequency (2MHz), tying it to ground forces the freq uency
to run at 0.67 times its normal frequency (1MHz).
PV
IN
(Pins 4, 5, 27, 28, 35, 36): Power V
IN
. Input voltage
to the on chip power MOSFETs. Must be closely decoupled
to PGND.
SW (Pins 6, 7, 8, 9, 23, 24, 25, 26): Switch Node Con-
nection to the Inductor. This pin swings from PV
IN
to
PGND.
MODE (Pin 10): Mode Select Input. Tying this pin high
enables Burst Mode operation. Tying this pin low enables
force continuous operation. Tying it to V
IN
/2 enables pulse-
skipping operation.
CLKIN (Pin 11): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with a
50k resistor. The phase-locked-loop will force the internal
top power PMOS turn on to be synchronized with the
rising edge of the CLKIN signal. Connect this pin to SV
IN
to enable spread spectrum modulation. During external
synchronization, make sure the PLLLPF pin is not tied to
V
IN
or GND.
PHMODE (Pin 12): Phase Selector Input. This pin deter-
mines the phase relationship between the internal oscil-
lator and CLKOUT. Tie it high for 2-phase operation, tie it
low for 3-phase operation, and tie it to V
IN
/2 for
4-phase operation.
PGND (Pins 13-19): Power Ground. Return path of internal
N-channel power MOSFETs. Connect this pin with the (–)
terminals of C
IN
and C
OUT
.
MGN (Pin 20): Margining Pin. Tying this pin to a voltage
between 0.5V and SV
IN
– 0.5V disables the margining
function and allows normal operation. Tying it high enables
positive margining (5, 10, or 15%). Tying it low enables
negative margining (–5, –10, or –15%).
BSEL (Pin 21): Margining Bit Select Pin. Tying BSEL low
selects ±5%, tying it high selects ±10%. Tying it to V
IN
/2
selects ±15%.
PGOOD (Pin 22): Output Power GOOD with Open-Drain
Logic. PGOOD is pulled to ground when the voltage on
the V
FB
pin is not within ±10% of its set point. Disabled
during margining and during slave mode operation (V
FB
tied to V
IN
).
V
FB
(Pin 29): Input to the error amplifi er that compares
the feedback voltage to the internal 0.6V reference voltage.
This pin is normally connected to a resistive divider from
the output voltage. In PolyPhase operation, tying V
FB
to
SV
IN
disables its own internal error amplifi er and connects
the master’s I
TH
voltage to its current comparator.
TRACK (Pin 30): Track Input Pin. This allows the user to
control the rise time of the output. Putting a voltage below
0.57V on this pin bypasses the reference input into the er-
ror amplifi er and servos the V
FB
pin to the TRACK voltage.
Above 0.57V, the tracking function stops and the internal
reference again controls the error amplifi er. During shut-
down, if TRACK is not tied to SV
IN,
then TRACK’s voltage
needs to be below 0.18V before the chip shuts down even
though RUN is already low. Do not fl oat this pin.
I
TH
(Pin 32): Error Amplifi er Output and Switching
Regulator Compensation Point. The current comparator’s
threshold increases with this control voltage. The normal
voltage range of this pin is from 0V to 1.5V. It’s also the
positive input to the internal I
TH
differential amplifi er. Tying
I
TH
to SV
IN
enables the internal compensation.
I
THM
(Pin 33): Negative Input to the Internal I
TH
Differential
Amplifi er. Tie this pin to SGND for single phase operation.
For PolyPhase, tie the master’s I
THM
to SGND while con-
necting all of the I
THM
pins together.
SV
IN
(Pin 34): Signal Input Voltage. Connect this pin to
PV
IN
through a 1Ω and 0.1μF lowpass fi lter.
RUN (Pin 37): Run Control Input. Tying this pin above
1.5V turns on the part.
CLKOUT (Pin 38): Output Clock Signal for PolyPhase
Operation. The phase of CLKOUT is determined by the
state of the PHMODE pin.
Exposed Pad (Pin 39): Power Ground. Must be connected
to electrical ground on PCB.
PIN FUNCTIONS