Datasheet

LTC3413
12
3413fc
APPLICATIONS INFORMATION
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (PV
IN
, SV
IN
, V
OUT
, PGND, SGND or any other DC rail
in your system).
5. Connect the V
FB
pin directly to the V
OUT
pin.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3413. Check the following in your layout.
1. A ground plane is recommended. If a ground plane
layer is not used, the signal and power grounds should
be segregated with all small-signal components returning
to the SGND pin at one point which is then connected to
the PGND pin close to the LTC3413.
2. Connect the (+) terminal of the input capacitor(s), C
IN
, as
close as possible to the PV
IN
pin. This capacitor provides
the AC current into the internal power MOSFETs.
R
PG
100k
R
ITH
5.11k
R
OSC
309k
*VISHAY DALE IHLP-2525CZ-01 0.47μH
**TDK C4532X5R0J107M
R
SS
4.7M
C
SS
330pF X7R
C
ITH
2200pF
X7R
C
C
100pF
PGOOD
SV
IN
PGOOD
I
TH
V
FB
R
T
V
REF
RUN/SS
SGND
PV
IN
SW
SWV
FB
PGND
PGND
SW
SW
PV
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC3413
L1*
0.47μH
C
IN1
**
100μF
C
IN2
**
100μF
C
OUT
**
100μF
s2
GND
3413 F03
V
OUT
1.25V
±3A
V
IN
2.5V
Figure 3. One-Half V
REF
, ±3A DDR Memory Termination Supply at 1MHz
(Effi ciency Curve is Shown in Figure 1b)