Datasheet

LTC3412A
14
3412afe
When a load step occurs, V
OUT
immediately shifts by an
amount equal to ∆I
LOAD(ESR)
, where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot
or ringing that would indicate a stability problem. The I
TH
pin external components and output capacitor shown in
Figure 1 will provide adequate compensation for most
applications.
Design Example
As a design example, consider using the LTC3412A in an
application with the following specifications:
V
IN
= 3.3V, V
OUT
= 2.5V, I
OUT(MAX)
= 3A,
I
OUT(MIN)
= 100mA, f = 1MHz.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
R k k
OSC
= =
3 08 10
1 10
10 298
11
6
. •
•
–
Use a standard value of 294k. Next, calculate the inductor
value for about 40% ripple current at maximum V
IN
:
L =
2.5V
(1MHz)(1.2A)
⎛
⎝
⎜
⎞
⎠
⎟
1 –
2.5V
3.3V
⎛
⎝
⎜
⎞
⎠
⎟
= 0.51µH
Using a 0.47µH inductor results in a maximum ripple
current of:
ΔI
L
=
2.5V
(1MHz)(0.47µH)
⎛
⎝
⎜
⎞
⎠
⎟
1 –
2.5V
3.3V
⎛
⎝
⎜
⎞
⎠
⎟
= 1.29A
C
OUT
will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100µF ceramic capacitors will be used.
C
IN
should be sized for a maximum current rating of:
I
RMS
= (3A)
2.5V
3.3V
⎛
⎝
⎜
⎞
⎠
⎟
3.3V
2.5V
– 1= 1.29A
RMS
Decoupling the PV
IN
and SV
IN
pins with two 22µF capaci-
tors is adequate for most applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2 and R3. The
voltage on pin MODE will be set to 0.50V by the resistor
divider consisting of R2 and R3. According to the graph
of Minimum Peak Inductor Current vs Burst Clamp Volt-
age in the Typical Performance Characteristics section, a
burst clamp voltage of 0.5V will set the minimum inductor
current, I
BURST
, to approximately 1.1A.
If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
R R k
R
R
V
V
2 3 185
1
2
3
0 8
0 50
+ =
+ =
.
.
The two equations shown above result in the following
values for R2 and R3: R2 = 69.8k , R3 = 115k. The value
of R1 can now be determined by solving the following
equation.
1
1
185
2 5
0 8
1 392
+ =
=
R
k
V
V
R k
.
.
A value of 392k will be selected for R1. Figure 4 shows
the complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3412A. Check the following in your layout:
1.
A
ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3412A.
2.
C
onnect the (+) terminal of the input capacitor(s), C
IN
, as
close as possible to the PV
IN
pin. This capacitor provides
the AC current into the internal power MOSFETs.
ApplicAtions inForMAtion