Datasheet

LTC3411
14
3411fb
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
The I
TH
external components shown in the Figure 1 circuit
will provide an adequate starting point for most applica-
tions. The series R-C fi lter sets the dominant pole-zero
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1μs
to 10μs will produce output voltage and I
TH
pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
OUT
im-
mediately shifts by an amount equal to ΔI
LOAD
• ESR, where
ESR is the effective series resistance of C
OUT
. ΔI
LOAD
also
begins to charge or discharge C
OUT
generating a feedback
error signal used by the regulator to return V
OUT
to its
steady-state value. During this recovery time, V
OUT
can
be monitored for overshoot or ringing that would indicate
a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
C
F
can be added to improve the high frequency response,
as shown in Figure 5. Capacitor C
F
provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V
IN
drops toward V
OUT
, the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
APPLICATIONS INFORMATION
PV
IN
LTC3411
PGOOD
PGOOD
SW
SV
IN
SYNC/MODE
V
FB
I
TH
SHDN/R
T
L1
D1
OPTIONAL
V
IN
2.5V
TO 5.5V
SGND PGND
R5
C
F
R
T
R
C
R1
R2
3411 F05
C
C
C
ITH
C5
V
OUT
C
IN
+
+
C6
PGND
SGND
PGND
SGND SGND SGND SGNDGND
PGND PGND
C
OUT
R6
C8
SGND
Figure 5. LTC3411 General Schematic