Datasheet

LTC3411A
17
3411afc
For more information www.linear.com/LTC3411A
applicaTions inForMaTion
For cost reasons, a ceramic capacitor will be used. C
OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
C
OUT
≈ 2.5
1.25A
1MHz • (5% • 2.5V)
= 25µF
The closest standard value is 22µF. Since the output
impedance of a Li-Ion battery is very low, C
IN
is typically
10µF. In noisy environments, decoupling SV
IN
from PV
IN
with an R6/C8 filter of 1Ω/0.1µF may help, but is typically
not needed.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2µA with the 0.8V feedback voltage makes R1~400k. A close
standard 1% resistor value is 412k. Then R2 is 887k.
The compensation should be optimized for these compo
-
nents by examining the load step response but a good place
to start for the LTC3411A is with a 12.1kΩ and 680pF filter
.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
The PGOOD pin is a common drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
The circuit on page 1 of this data sheet shows the complete
schematic for this design example.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3411A. These items are also illustrated graphically
in the layout diagram of Figure 7. Check the following in
your layout:
1. Does the capacitor C
IN
connect to the power V
IN
(Pin 6)
and power GND (Pin 5) as close as possible? This capacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C
OUT
and L1 closely connected? The (–) plate of
C
OUT
returns current to PGND and the (–) plate of C
IN
.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground line terminated
near SGND (Pin 3). The feedback signal V
FB
should be
routed away from noisy components and traces, such as
the SW line (Pin 4), and its trace should be minimized.
4. Keep sensitive components away from the SW pin. The
input capacitor C
IN
, the compensation capacitor C
C
and
C
ITH
and all the resistors R1, R2, R
T
, and R
C
should be
routed away from the SW trace and the inductor L1. The
SW pin pad should be kept as small as possible.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small signal
components returning to the SGND pin at one point which
is then connected to the PGND pin.
6. Flood all unused areas on all layers with copper. Flood
-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
one of the input supplies: P
V
IN
, PGND, SV
IN
or SGND.
Figure 7. LTC3411A Layout Diagram (See Board Layout Checklist)
PV
IN
LTC3411A
PGND
SW
SV
IN
SGND
PGOODPGOOD
V
FB
SYNC/MODE
I
TH
SHDN/R
T
L1
V
IN
BMPS
V
IN
V
OUT
R5
R
T
R
C
C
ITH
R1R2
3411A F07
C
C
BOLD LINES INDICATE HIGH CURRENT PATHS
C
IN
C
OUT
C4