Datasheet

12
LTC3410
3410fb
APPLICATIO S I FOR ATIO
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Figure 4a. LTC3410 Layout Diagram
Figure 5a. LTC3410 Suggested Layout
RUN
LTC3410
GND
SW
L1
R2
R1
C
FWD
BOLD LINES INDICATE HIGH CURRENT PATHS
V
IN
V
OUT
3410 F04a
4
6
5
1
3
+
–
2
V
FB
V
IN
C
IN
C
OUT
RUN
LTC3410-1.875
GND
SW
L1
BOLD LINES INDICATE HIGH CURRENT PATHS
V
IN
V
OUT
3410 F04b
4
6
5
1
3
+
–
2
V
OUT
V
IN
C
IN
C
OUT
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C
OUT
and ground.
3. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the (–) plates of C
IN
and C
OUT
as close as possible.
5. Keep the switching node, SW, away from the sensitive
V
FB
node.
Figure 4b. LTC3410-1.875 Layout Diagram
LTC3410
GND
3410 F05a
PIN 1
V
OUT
V
IN
VIA TO V
OUT
SW
VIA TO V
IN
VIA TO GND
C
OUT
C
IN
L1
R2
C
FWD
R1
LTC3410-
1.875
3410 F05b
PIN 1
V
OUT
V
IN
SW
VIA TO V
IN
C
OUT
C
IN
L1
Figure 5b. LTC3410 Fixed Output Voltage
Suggested Layout
Design Example
As a design example, assume the LTC3410 is used in a
single lithium-ion battery-powered cellular phone
application. The V
IN
will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.3A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
3V. With this information we can calculate L using
Equation (1),
L
fI
V
V
V
L
OUT
OUT
IN
=
()
∆
()
−
⎛
⎝
⎜
⎞
⎠
⎟
1
13()