Datasheet

LTC3409
3
3409fc
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3409E is guaranteed to meet performance specifi cations
from 0°C to 70°C. Specifi cations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3409I is guaranteed to meet
specifi ed performance over the full –40°C to 85°C operating temperature
range.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
LTC3409: T
J
= T
A
+ (P
D
)(43°C/W)
This IC includes overtemperature protection that is intended to protect the
device during momentary overload conditions. Overtemperature protection
becomes active at a junction temperature greater than the maximum
operating junction temperature. Continuous operation above the specifi ed
maximum operating junction temperature may impair device reliability.
Note 4: The LTC3409 is tested in a proprietary test mode that connects V
FB
to the output of the error amplifi er.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: ΔV
OVL
is the amount V
FB
must exceed the regulated feedback
voltage.
Note 7: Determined by design, not production tested.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
S
Input DC Bias Current
Active Mode
Sleep Mode
Shutdown
(Note 5)
V
OUT
= 90%, I
LOAD
= 0A
V
OUT
= 103%, I
LOAD
= 0A
V
RUN
= 0V, V
IN
= 5.5V
350
65
0.1
475
120
1
μA
μA
μA
f
OSC
Nominal Oscillator Frequency SYNC = GND
SYNC = V
IN
●
●
0.9
1.8
1.7
2.6
2.1
3.0
MHz
MHz
SYNC TH SYNC Threshold When SYNC Input is Toggling (Note 7) 0.63 V
SYNC f
MIN
Minimum SYNC Pin Frequency 1 MHz
SYNC f
MAX
Maximum SYNC Pin Frequency 3 MHz
SYNC PW Minimum SYNC Pulse Width 100 ns
t
SS
Soft-Start Period RUN↑ 1ms
SYNC t
O
SYNC Timeout Delay from Removal of EXT CLK Until Fixed
Frequency Operation Begins (Note 7)
30 μs
R
PFET
R
DS(ON)
of P-Channel FET I
SW
= 100mA, Wafer Level
I
SW
= 100mA, DD Package
0.33
0.35
Ω
Ω
R
NFET
R
DS(ON)
of N-Channel FET I
SW
= 100mA, Wafer Level
I
SW
= 100mA, DD Package
0.22
0.25
Ω
Ω
I
LSW
SW Leakage V
RUN
= 0V, V
SW
= 0V or 5V, V
IN
= 5V ±0.1 ±3 μA
The ● denotes specifi cations which apply over the full operating
temperature range, otherwise specifi cations are T
A
= 25°C. V
IN
= 2.2V unless otherwise specifi ed.
ELECTRICAL CHARACTERISTICS