Datasheet

12
LTC3405
3405fa
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3405. These items are also illustrated graphically in
Figures 9 and 10. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V
IN
trace should be kept short, direct and
wide.
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C
OUT
and ground.
3. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
V
FB
node.
Design Example
As a design example, assume the LTC3405 is used in a
single lithium-ion battery-powered cellular phone
application. The V
IN
will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.25A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
2.5V. With this information we can calculate L using
equation (1),
L
fI
V
V
V
L
OUT
OUT
IN
=
()
∆
()
−
⎛
⎝
⎜
⎞
⎠
⎟
1
1
(3)
APPLICATIO S I FOR ATIO
WUUU
Figure 9. LTC3405 Layout Diagram
RUN
LTC3405
GND
SW
6
L1
R2
R3*
R1
C
FWD
BOLD LINES INDICATE HIGH CURRENT PATHS
*ADD R3 FOR APPLICATIONS USING A CERAMIC C
OUT
V
IN
V
OUT
3405 F09
4
5
1
3
+
–
2
MODE
V
FB
V
IN
C
IN
+
–
C
OUT
LTC3405
GND
3405 F10
*ADD R3 WHEN USING CERAMIC C
OUT
PIN 1
V
OUT
V
IN
V
FB
VIA TO V
OUT
SW
VIA TO V
IN
VIA TO SW NODE VIA TO GND
C
OUT
C
IN
L1
R2
C
FWD
R3* R1
Figure 10. LTC3405 Suggested Layout