Datasheet

10
LTC3405
3405fa
APPLICATIO S I FOR ATIO
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In pulse skipping mode, the LTC3405 is stable with a 4.7µF
ceramic output capacitor with V
IN
≤ 4.2V. For single Li-Ion
applications operating in pulse skipping mode, the circuit
shown in Figure 6 can be used
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
V
IN
C
IN
2.2µF
CER
V
IN
2.7V
TO 4.2V
LTC3405
RUN
MODE
3
4.7µH
22pF
887k
1M
3405 F06
5
4
6
1
2
SW
V
FB
GND
C
OUT1
4.7µF
CER
V
OUT
1.5V
Figure 6. Using All Ceramic Capacitors in Pulse Skipping Mode
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
VV
R
R
OUT
=+
⎛
⎝
⎜
⎞
⎠
⎟
08 1
2
1
.
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 7.
Figure 7. Setting the LTC3405 Output Voltage
Figure 8. Power Lost vs Load Current
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3405 circuits: V
IN
quiescent current and I
2
R
losses. The V
IN
quiescent current loss dominates the
efficiency loss at very low load currents whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 8.
V
FB
GND
LTC3405
0.8V ≤ V
OUT
≤ 5.5V
R2
R1
3405 F07
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
LOAD CURRENT (mA)
0.1
POWER LOST (W)
10
1000
1
0.1
0.01
0.001
0.0001
3405 F08
1 100
V
OUT
= 1.8V
V
IN
= 3.6V
V
OUT
= 3.3V
V
OUT
= 2.5V
V
OUT
= 1.3V
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both