Datasheet

LTC3375
20
3375fc
For more information www.linear.com/3375
operaTion
t
SU, DAT
t
HD, STA
t
HD, DAT
SDA
SCL
t
SU, STA
t
HD, STA
t
SU, STO
3375 F03
t
BUF
t
LOW
t
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
r
t
f
t
SP
ACK ACK
1 2 3
ADDRESS WR
4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
0 1 1 0 1 0 0 0
0 1 1 0 1 0 0 0
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
ACK
STOPSTART
SDA
SCL
DATA BYTE A DATA BYTE B
Figure 3. I
2
C Bus Operation
I
2
C Interface
The LTC3375 may communicate with a bus master using the
standard I
2
C 2-wire interface. The timing diagram (Figure3)
shows the relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is
not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus accelerator, are required
on these lines. The LTC3375 is both a slave receiver and
slave transmitter. The I
2
C control signals, SDA and SCL
are scaled internally to the V
CC
supply.
The I
2
C port has an undervoltage lockout on the V
CC
pin.
When V
CC
is below 1.8V, the I
2
C serial port is cleared and
the LTC3375 registers are set to their default configurations.
I
2
C Bus Speed
The I
2
C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure cor-
rect operation when addressed from the I
2
C compatible
master device.
I
2
C Start and Stop Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3375, the master may transmit a STOP condition which
commands the LTC3375 to act upon its new command
set. A STOP condition is sent by the master by transition
-
ing SDA from LOW to HIGH while SCL is HIGH. The bus
is then free for communication with another I
2
C device.
I
2
C Byte Format
Each byte sent to or received from the LTC3375 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3375
most significant bit (MSB) first.
I
2
C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3375 is written
to (write address), it acknowledges its write address as
well as the subsequent two data bytes. When it is read
from (read address), the LTC3375 acknowledges its read
address only. The bus master should acknowledge receipt
of information from the LTC3375.
An acknowledge (active LOW) generated by the LTC3375
lets the master know that the latest byte of information was
received. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH)
during the acknowledge clock cycle. The LTC3375 pulls
down the SDA line during the write acknowledge clock
pulse so that it is a stable LOW during the HIGH period
of this clock pulse.