Datasheet

LTC3375
25
3375fc
For more information www.linear.com/3375
operaTion
After detecting an external clock on the first rising edge of
the SYNC pin, the PLL starts up at the current frequency
being programmed by the RT pin. The internal PLL then
requires a certain number of periods to gradually settle
until the frequency at SW matches the frequency and
phase of SYNC.
When the external clock is removed the LTC3375 needs
approximately 5µs to detect the absence of the external
clock. During this time, the PLL will continue to provide
clock cycles before it recognizes the lack of a SYNC input.
Once the external clock removal has been identified, the
oscillator will gradually adjust its operating frequency to
match the desired frequency programmed at the RT pin.
V
CC
Shunt Regulator
The LTC3375 has the control circuitry to regulate the output
of an N-type device. The circuit should be connected as
shown in Figures 6a and 6b. The voltage at FBV
CC
will servo
to 1.20V and V
CC
can be programmed between 2.7V and
5.5V. The N-type device can be used to regulate a lower
voltage at V
CC
while being powered from a high voltage
supply. The N-type device must be chosen so that it can
handle the power dissipated in regulating V
CC
. The internal
circuitry of the LTC3375 can only pull-down on the V
SHNT
node. A pull-up resistor is required for positive gate drive.
If V
CC
is incorrectly programmed or a current load at V
CC
causes V
SHNT
to go above 6.1V (typical), then V
SHNT
will
be internally clamped and V
CC
may lose regulation.
If the use of the V
CC
regulator is not desired, then V
CC
should be tied to an external DC voltage source and a
decoupling capacitor. FBV
CC
and V
SHNT
should be tied
to ground.
Watchdog Timer
The watchdog circuit monitors a microprocessor’s activity.
The microprocessor is required to change the logic state
of the WDI pin at least once every 1.5 seconds (typical)
in order to clear the watchdog timer and prevent the WDO
pin from signaling a timeout.
The watchdog timer begins running immediately after a
power-on reset. The watchdog timer will continue to run
until a transition is detected on the WDI input. During
this time WDO will be in a Hi-Z state. Once the watchdog
timer times out, WDO will be pulled low and the reset
timer is started. WDO being pulled low may be used to
force a reset on the controlling microprocessor. If no WDI
transition is received when the reset timer times out, after
200ms (typical), WDO will again become Hi-Z and the 1.5
seconds watchdog reset time will begin again. If a transition
is received on the WDI input during the watchdog timeout
period, then WDO will become Hi-Z immediately after the
WDI transition and the 1.5 seconds watchdog reset time
will begin at that point.