Datasheet

LTC3300-2
28
33002f
For more information www.linear.com/LTC3300-2
APPLICATIONS INFORMATION
External Sense Resistor Selection
The external current sense resistors for both primary
and secondary windings set the peak balancing current
according to the following formulas:
R
SENSE|PRIMARY
=
50mV
I
PEAK _PRI
R
SENSE|SECONDARY
=
50mV
I
PEAK _ SEC
Balancer Synchronization
Due to the stacked configuration of the individual synchro-
nous flyback power circuits and the interleaved nature of
the gate drivers, it is possible at higher balance currents
for adjacent and/or penadjacent balancers within a group
of six to sync up. The synchronization will typically be to
the highest frequency of any active individual balancer and
can result in a slightly lower balance current in the other
affected balancer(s). This error will typically be very small
provided that the individual cells are not significantly out
of balance voltage-wise and due to the matched I
PEAK
/
I
ZERO
’s and matched power circuits. Balancer synchro-
nization can be reduced by lowpass filtering the primary
and/or
secondary current sense signals with a simple RC
network as shown in Figure 9. A good starting point for
the RC time constant is one-tenth of the on-time of the
associated switch (primary or secondary). In the case
of I
PEAK
sensing, phase lag associated with the lowpass
filter will result in a slightly lower voltage seen by the
LTC3300-2 compared to the true sense resistor voltage.
This error can be compensated for by selecting the R value
to add back this same drop using the typical current value
of
20µA out of the LTC3300-2 current sense pins at the
comparator trip point.
Setting Appropriate Max On-Times
The primary and secondary winding volt-second clamps
are intended to be used as a current runaway protection
feature and not as a substitute means of current control
replacing the sense resistors. In order to not interfere with
normal I
PEAK
/I
ZERO
operation, the maximum on times must
be set longer than the time required to ramp to I
PEAK
(or
I
ZERO
) for the minimum cell voltage seen in the application:
t
ON(MAX)|PRIMARY
> L
PRI
• I
PEAK_PRI
/V
CELL(MIN)
t
ON(MAX)|SECONDARY
> L
PRI
• I
PEAK_SEC
• T/(S • V
CELL(MIN)
)
These can be further increased by 20% to account for
manufacturing tolerance in the transformer winding
inductance and by 10% to account for I
PEAK
variation.
External FET Selection
In addition to being rated to handle the peak balancing
current, external NMOS transistors for both primary and
secondary windings must be rated with a drain-to-source
breakdown such that for the primary MOSFET:
V
DS(BREAKDOWN)|MIN
> V
CELL
+
V
STACK
+ V
DIODE
T
= V
CELL
1+
S
T
⎛
⎝
⎜
⎞
⎠
⎟
+
V
DIODE
T
and for the secondary MOSFET:
V
DS(BREAKDOWN)|MIN
> V
STACK
+ T V
CELL
+ V
DIODE
( )
= V
CELL
S+ T
( )
+ T V
DIODE
where S is the number of cells in the secondary winding
stack and 1:T is the transformer turns ratio from primary
to secondary. For example, if there are 12 Li-Ion cells in
the secondary stack and using a turns ratio of 1:2, the
primary FETs would have to be rated for greater than 4.2V
(1 + 6) + 0.5 = 29.9V and the secondary FETs would have
to be rated for greater than 4.2V (12 + 2) + 2V = 60.8V.
LTC3300-2
n = 2 TO 6
20µA
R
C
R
SNS
33002 F09
G1P/GnP/G1S/GnS
I1P/InP/I1S/InS
V
–
/Cn – 1/V
–
/V
–
Figure 9. Using an RC Network to Filter
Current Sense Inputs to the LT C 3300-2