LTC3300-2 Addressable High Efficiency Bidirectional Multicell Battery Balancer DESCRIPTION FEATURES n n n n n n n n n n n Bidirectional Synchronous Flyback Balancing of Up to 6 Li-Ion or LiFePO4 Cells in Series Up to 10A Balancing Current (Set by Externals) Integrates Seamlessly with the LTC680x Family of Multicell Battery Stack Monitors Bidirectional Architecture Minimizes Balancing Time and Power Dissipation Up to 92% Charge Transfer Efficiency Stackable Architecture Enables >800V Systems Uses Simpl
LTC3300-2 ABSOLUTE MAXIMUM RATINGS (Note 1) Total Supply Voltage (C6 to V–)..................................36V Input Voltage (Relative to V–) C1 ............................................................ –0.3V to 6V I1P ........................................................ –0.3V to 0.3V I1S, I2S, I3S, I4S, I5S, I6S..................... –0.3V to 0.3V CSBI, SCKI, SDI........................................ –0.3V to 6V VREG, SDO................................................ –0.3V to 6V RTONP, RTONS.
LTC3300-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V, C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
LTC3300-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V, C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
LTC3300-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V, C3 = 10.8V, C2 = 7.2V, C1 = 3.6V, V– = 0V, unless otherwise noted.
LTC3300-2 TYPICAL PERFORMANCE CHARACTERISTICS 1.06 C6 = 21.6V IQ(ACTIVE)/IQ(ACTIVE AT 25°C) 2.05 VCELL(MIN) (V) 1.95 1.00 14 12 0.98 TYP = 740µA TYP = 560µA TYP = 250µA TYP = 70µA TYP = 60µA TYP = –70µA 0.96 0 0.94 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 0 5.2 1.80 –50 –25 5.0 CELL VOLTAGE RISING VREG Load Regulation 4.70 TA = 25°C 4.69 VREG Voltage vs Temperature IVREG = 10mA 4.68 4.9 C6 = 36V 4.7 4.6 CELL VOLTAGE FALLING 4.4 4.8 4.66 C6 = 9V VREG (V) 4.
LTC3300-2 TYPICAL PERFORMANCE CHARACTERISTICS VRTONP, VRTONS vs External Resistance 1.236 TA = 25°C unless otherwise specified. WDT Pin Current vs Temperature 85 TA = 25°C RTONS = 15k BALANCING WDT = 0.5V 1.224 80 VRTONP, VRTONS (V) WDT Pin Current vs RTONS 240 200 1.212 75 SECONDARY OV WDT = 2V 1.188 VRTONS IWDT (µA) IWDT (µA) 160 1.200 70 VRTONP 10 RTONP, RTONS RESISTANCE (kΩ) 65 –50 –25 100 0 VZERO_P, VZERO_S (mV) 8.0 0 SECONDARY –5.0 –7.
LTC3300-2 TYPICAL PERFORMANCE CHARACTERISTICS Balancer Efficiency vs Cell Voltage Balance Current vs Cell Voltage 2.7 DC2064A DEMO BOARD ICHARGE = IDISCHARGE = 2.5A FOR 12-CELL STACK ONLY 91 90 89 DISCHARGE, 12-CELL STACK DISCHARGE, 6-CELL STACK CHARGE, 6-CELL STACK CHARGE, 12-CELL STACK 2.8 3.0 CHARGE, 12-CELL STACK 2.6 92 3.2 3.4 3.6 3.8 VOLTAGE PER CELL (V) 4.0 BALANCE CURRENT (A) CHARGE TRANSFER EFFICIENCY (%) 93 TA = 25°C unless otherwise specified. DISCHARGE, 12-CELL STACK 2.5 2.
LTC3300-2 PIN FUNCTIONS Note: The convention adopted in this data sheet is to refer to the transformer winding paralleling an individual battery cell as the primary and the transformer winding paralleling multiple series-stacked cells as the secondary, regardless of the direction of energy transfer.
LTC3300-2 PIN FUNCTIONS C1, C2, C3, C4, C5, C6 (Pins 24, 27, 30, 33, 36, 39): C1 through C6 connect to the positive terminals of battery cells 1 through 6. Connect the negative terminal of battery cell 1 to V–. BOOST+ (Pin 40): Boost+ Pin. Connects to the anode of the external flying capacitor used for generating sufficient gate drive necessary for balancing the topmost battery cell in a given LTC3300-2 sub-stack. A Schottky diode from C6 to BOOST+ is needed as well.
LTC3300-2 BLOCK DIAGRAM 48 41 VREG C6 VOLTAGE REGULATOR V– 40mA MAX 4.
LTC3300-2 TIMING DIAGRAM Timing Diagram of the Serial Interface t4 t1 t2 t3 t6 t7 SCKI SDI t5 CSBI t8 SDO 33002 TD 33002f 12 For more information www.linear.
LTC3300-2 OPERATION Battery Management System (BMS) The LTC3300-2 multicell battery cell balancer is a key component in a high performance battery management system (BMS) for series-connected Li-Ion cells. It is designed to operate in conjunction with a monitor, a charger, and a microprocessor or microcontroller (see Figure 1).
LTC3300-2 OPERATION TOP OF STACK ICHARGE + C6 C5 C4 LTC3300-2 BALANCER C3 DIGITAL ISOLATOR C2 V– C1 CELL N + CELL N – 1 + CELL N – 2 + CELL N – 3 + CELL N – 4 + CELL N – 5 + C6 C5 C4 LTC3300-2 C3 BALANCER DIGITAL ISOLATOR CN C2 V– C1 CELL N – 6 + CELL N – 7 + C11 C12 ILOAD C10 C9 C8 C7 C6 LTC6803-2 MONITOR C5 C4 CELL N – 8 C3 + CELL N – 9 + CELL N – 10 + C2 – C1 V C11 C12 CELL N – 11 DIGITAL ISOLATOR • • • CHARGER + V– C6 LTC3300-2 BALANCER DIGITAL ISOLATOR C5
LTC3300-2 OPERATION Synchronous Flyback Balancer charge from the highest voltage cell(s) in the stack to other lower voltage cells in the stack (active balancing). This can be very efficient (in terms of charge recovery) for the case where only a few cells in the overall stack are high, but will be very inefficient (and time consuming) for the case where only a few cells in the overall stack are low.
LTC3300-2 OPERATION Cell Discharging (Synchronous) When discharging is enabled for a given cell, the primary side switch is turned on and current ramps in the primary winding of the transformer until the programmed peak current (IPEAK_PRI) is detected at the In P pin. The primary side switch is then turned off, and the stored energy in the transformer is transferred to the secondary-side cells causing current to flow in the secondary winding of the transformer.
LTC3300-2 OPERATION 6.8Ω 0.1µF BOOST– BOOST+ UP TO • CELL 12 •• C6 10µF 1:1 • 10µH 10µH • G6P + CELL 6 I6P 25mΩ G6S I6S 25mΩ C5 10µF 1:1 • 10µH 10µH • G5P + I5P CELL 5 25mΩ G5S I5S 25mΩ C4 LTC3300-2 • • • • • • C3 C2 10µF 1:1 • 10µH 10µH • G2P A4 A3 A2 A1 A0 SERIAL COMMUNICATION RELATED PINS + CELL 2 I2P 25mΩ G2S CSBI SCKI SDI SDO I2S 25mΩ C1 WDT 10µF 1:1 • 10µH 10µH • G1P + I1P CELL 1 25mΩ VREG G1S BOOST I1S 25mΩ CTRL 10µF RTONP RTONS 22.6k V– 6.
LTC3300-2 OPERATION Balancing High Voltage Battery Stacks TOP Balancing series connected batteries which contain >>12 cells in series requires interleaving of the transformer secondary connections in order to achieve full stack balancing while limiting the breakdown voltage requirements of the primary- and secondary-side power FETs. Figure 4 shows typical interleaved transformer connections for a multicell battery stack in the generic sense, and Figure 5 for the specific case of an 18-cell stack.
LTC3300-2 OPERATION 0.1µF 6.
LTC3300-2 OPERATION Gate Drivers/Gate Drive Comparators All secondary-side gate drivers (G1S through G6S) are powered from the VREG output, pulling up to 4.8V when on and pulling down to V– when off. All primary-side gate drivers (G1P through G6P) are powered from their respective cell voltage and the next cell voltage higher in the stack (see Table 1).
LTC3300-2 OPERATION sipation. The internal component of the DC load current is dominated by the average gate driver current(s) (G1S through G6S), each approximated by C • V • f, where C is the gate capacitance of the external NMOS transistor, V = VREG = 4.8V, and f is the frequency that the gate driver output is running at. FET manufacturers usually specify the C • V product as Qg (gate charge) measured in coulombs at a given gate drive voltage.
LTC3300-2 OPERATION balance command remains stored in memory, and active balancing will resume where it left off if the stack voltage subsequently falls to a safer level. Secondary Winding OVP Function (via WDT pin) The precision current source pull-down on the WDT pin during balancing can be used to construct an accurate secondary winding OVP protection circuit as shown in Figure 6c.
LTC3300-2 OPERATION 0.1µF 6.8Ω • • • BOOST– BOOST+ UP TO CELL 12 EACH 1:1 • C6 10µH 10µF • G6P I6P + C5 25mΩ CELL 6 10µH 10µF • G5P I5P + C4 25mΩ CELL 5 10µH 10µF • G4P I4P + LTC3300-2 C3 25mΩ CELL 4 10µH 10µF • G3P I3P + C2 25mΩ CELL 3 10µH 10µF G2P A4 A3 A2 A1 A0 SERIAL COMMUNICATION RELATED PINS • I2P + C1 CSBI SCKI SDI SDO 25mΩ CELL 2 10µH 10µF • G1P WDT I1P 25mΩ G1S VREG I1S G2S-G6S I2S-I6S CTRL V– RTONP RTONS BOOST 10µF 22.6k NC + CELL 1 25mΩ 33002 F07 6.
LTC3300-2 OPERATION SERIAL PORT OPERATION Data Link Layer Overview The LTC3300-2 has an SPI bus compatible serial port. Devices can be connected in parallel, using digital isolators. Multiple devices are uniquely identified by a part address determined by the A0 to A4 pins. Physical Layer On the LTC3300-2, four pins comprise the serial interface: CSBI, SCKI, SDI and SDO. The SDO and SDI pins may be tied together, if desired, to form a single bidirectional port.
LTC3300-2 OPERATION Command Byte Write Balance Command All communication to the LTC3300-2 takes place with CSBI logic low. The first 8 clocked in data bits after a high-tolow transition on CSBI represent the command byte. The 8-bit command byte is written MSB first per Table 2. The first 5 bits must match the fixed pin-strapped address [A4 A3 A2 A1 A0] for the individual device, or all subsequent data will be ignored until CSBI transitions high and then low again.
LTC3300-2 OPERATION For nonsynchronous discharging of cell n, both the secondary winding gate drive and (zero) current sense amp are disabled. The secondary current will conduct either through the body diode of the secondary switch (if present) or through a substitute Schottky diode. The primary will only turn on again after the secondary winding Voltsec clamp times out.
LTC3300-2 OPERATION ror checking. Only the individual LTC3300-2 in the stack with the matching address will send out the status data. Note that the CRC bits in the Read Balance Status are inverted. This was done so that an “all zeros” readback is invalid. The first 6 bits of the read balance status indicate if there is sufficient gate drive for each of the 6 balancers.
LTC3300-2 APPLICATIONS INFORMATION External Sense Resistor Selection The external current sense resistors for both primary and secondary windings set the peak balancing current according to the following formulas: RSENSE|PRIMARY = 50mV Setting Appropriate Max On-Times IPEAK _PRI RSENSE|SECONDARY = 50mV IPEAK _ SEC Balancer Synchronization Due to the stacked configuration of the individual synchronous flyback power circuits and the interleaved nature of the gate drivers, it is possible at higher balanc
LTC3300-2 APPLICATIONS INFORMATION Good design practice recommends increasing this voltage rating by at least 20% to account for higher voltages present due to leakage inductance ringing. See Table 7 for a list of FETs that are recommended for use with the LTC3300-2.
LTC3300-2 APPLICATIONS INFORMATION Sizing the Cell Bypass Caps for Broken Connection Protection If a single connection to the battery stack is lost while balancing, the differential cell voltages seen by the LTC3300-2 power circuit on each side of the break can increase or decrease depending on whether charging or discharging and where the actual break occurred. The worst-case scenario is when the balancers on each side of the break are both active and balancing in opposite directions.
LTC3300-2 APPLICATIONS INFORMATION Supplementary Voltage Regulator Drive (>40mA) The 4.8V linear voltage regulator internal to the LTC3300-2 is capable of providing 40mA at the VREG pin. If additional current capability is required, the VREG pin can be backdriven by an external low cost 5V buck DC/DC regulator C6 LTC3300-2 IOUT > 40mA VIN CIN SW BUCK DC/DC FB GND L 5V VREG RFB2 COUT 4.8V LINEAR VOLTAGE REGULATOR V– RFB1 33002 F11 powered from C6 as shown in Figure 11.
LTC3300-2 APPLICATIONS INFORMATION Internal Protection Diodes Each pin of the LTC3300-2 has protection diodes to help prevent damage to the internal device structures caused by external application of voltages beyond the supply rails as shown in Figure 12. The diodes shown are conventional silicon diodes with a forward breakdown voltage of 0.5V. The unlabeled Zener diode structures have a reversebreakdown characteristic which initially breaks down at 9V then snaps back to a 7V clamping potential.
LTC3300-2 APPLICATIONS INFORMATION VREG LTC3300-2 47 46 45 44 43 40 WDT A4 SDO A3 SDI A2 SCKI A1 CSBI A0 BOOST BOOST+ CTRL RTONP 41 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 BOOST– RTONS 48 20 19 18 17 16 42 15 14 13 C6 G6P G6S I6P I6S 1 2 C5 G5P G5S I5P I5S C4 3 4 ZCLAMP G4P G4S I4P I4S 5 6 C3 G3P G3S I3P I3S C2 7 8 ZCLAMP G2P G2S I2P I2S 9 10 C1 G1P G1S I1P I1S 11 12 4Ω EXPOSED PAD 49 V– 21 33002 F12 Figure 12.
LTC3300-2 APPLICATIONS INFORMATION How to Calculate the CRC One simple method of computing an n-bit CRC is to perform arithmetic modulo-2 division of the n+1 bit characteristic polynomial into the m bit message appended with n zeros (m+n bits). Arithmetic modulo-2 division resembles normal long division absent borrows and carries.
LTC3300-2 APPLICATIONS INFORMATION “Ø” “Ø” D6B D5B CRC [3] D3B D1B CRC [3] D2A D5A CRC [2] D3A D1A CRC [2] D4B CRC [1] D2B CRC [1] D4A D6A “Ø” CRC [0] “Ø” CRC [0] 33002 F14 Figure 14. Combinational Logic Circuit Implementation of the CRC Calculator Serial Communication Using the LTC6803 and LTC6804 The LTC3300-2 is compatible with and convenient to use with all LTC monitor chips, such as the LTC6803 and LTC6804.
LTC3300-2 APPLICATIONS INFORMATION PCB Layout Considerations The LTC3300-2 is capable of operation with as much as 40V between BOOST+ and V–. Care should be taken on the PCB layout to maintain physical separation of traces at different potentials. The pinout of the LTC3300-2 was chosen to facilitate this physical separation. There is no more than 8.4V between any two adjacent pins with the exception of one instance (BOOST to BOOST–).
LTC3300-2 TYPICAL APPLICATIONS 6.8Ω 0.
LTC3300-2 TYPICAL APPLICATIONS TOP OF BATTERY STACK C5 C4 C3 C2 LTC3300-2 C1 ADDRESS = 00011 CSBI VREG SCKI SDI – SDO V + C6 DIGITAL ISOLATOR + + + CVREG4 + + + C5 C4 C3 LTC3300-2 C2 ADDRESS = 00010 C1 CSBI VREG SCKI SDI – SDO V C6 DIGITAL ISOLATOR + + + CVREG3 + + C5 C4 C3 LTC3300-2 C2 ADDRESS = 00001 C1 CSBI VREG SCKI SDI – SDO V + C6 DIGITAL ISOLATOR + + + CVREG2 + + + C5 C4 C3 LTC3300-2 C2 ADDRESS = 00000 C1 CSBI VREG SCKI SDI SDO V – C6 3V DIGITAL ISOLATOR V1+ V2+ CS MPU CLK VREG1
LTC3300-2 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UK Package 48-Lead Plastic QFN (7mm × 7mm) (Reference LTC DWG # 05-08-1704 Rev C) 0.70 ±0.05 5.15 ±0.05 5.50 REF 6.10 ±0.05 7.50 ±0.05 (4 SIDES) 5.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 ±0.10 (4 SIDES) 0.75 ±0.05 R = 0.10 TYP R = 0.115 TYP 47 48 0.40 ±0.
LTC3300-2 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. LXE Package 48-Lead Plastic Exposed Pad LQFP (7mm × 7mm) (Reference LTC DWG #05-08-1832 Rev C) 7.15 – 7.25 5.50 REF 1 48 37 36 0.50 BSC C0.30 5.50 REF 7.15 – 7.25 0.20 – 0.30 3.60 ±0.05 3.60 ±0.05 PACKAGE OUTLINE 24 XXYY LTCXXXX LX-ES Q_ _ _ _ _ _ e3 12 13 25 COMPONENT PIN “A1” 1.
LTC3300-2 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 12/13 Add new bullet Integrates Seamlessly with the LTC680x Family of Multicell Battery Stack Monitors 1 Change part number XF0036-EP135 to XF0036-EP13S 29 33002f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
LTC3300-2 TYPICAL APPLICATION LTC3300-2/LTC6804-2 Serial Communication Connections DATA LTC3300-2 ADDRESS = 00011 9 CELLS 4 DIGITAL ISOLATOR LTC6804-2 LTC3300-2 ADDRESS = 00010 SCKI SDI SDO CSBI ADDRESS = 0001 GPIO5 GPIO4 ISO IN GPIO3 LTC3300-2 ADDRESS = 00001 12 CELLS 12-CELL MODULE 2 4 12-CELL MODULE 1 DIGITAL ISOLATOR LTC6804-2 LTC3300-2 ADDRESS = 00000 SCKI SDI SDO CSBI ADDRESS = 0000 LTC6820 isoSPI GPIO5 GPIO4 ISO IN ISO SPI 4 GPIO3 33002 TA02 RELATED PARTS PART NUMBER DESCRIPTION
