Datasheet

LTC3260
10
3260fa
operaTion
(Refer to the Block Diagram)
Figure 2 shows the LDO
+
regulator application circuit.
The LDO
+
output voltage V
LDO
+
can be programmed by
choosing suitable values of R1 and R2 such that:
V
LDO
+
=1.2V •
R1
R2
+1






An optional capacitor of 10nF can be connected from the
BYP
+
pin to ground. This capacitor bypasses the internal
1.2V reference of the LTC3260 and improves the noise
performance of the LDO
+
. If this function is not used the
BYP
+
pin should be left floating.
negative by the charge pump circuitry. Soft-start circuitry
in the charge pump also provides soft-start functionality
for the LDO
–
and prevents excessive inrush currents.
Figure 3 shows the LDO
–
regulator application circuit.
The LDO
–
output voltage V
LDO
–
can be programmed by
choosing suitable values of R1 and R2 such that:
V
LDO
–
= –1.2V •
R1
R2
+1






When the inverting charge pump is in Burst Mode opera-
tion (MODE = high), the typical hysteresis on the V
OUT
pin is 2% of V
IN
voltage. The LDO
–
voltage should be set
high enough above V
OUT
in order to prevent LDO
–
from
entering dropout during normal operation.
An optional capacitor of 10nF can be connected from the
BYP
–
pin to ground. This capacitor bypasses the internal
–1.2V reference of the LTC3260 and improves the noise
performance of the LDO
–
. If this function is not used the
BYP
–
pin should be left floating.
In order to improve transient response, an optional
capacitor, C
ADJ
–
, may be used as shown in Figure 3. A
recommended value for C
ADJ
–
is 10pF. Experimentation
with capacitor values between 2pF and 22pF may yield
improved transient response.
Figure 2: Positive LDO Application Circuit
V
IN
1
0
LDO
+
EN
+
ADJ
+
GND
BYP
+
C
BYP
+
C
OUT
LTC3260
LDO
OUTPUT
R2
3260 F02
R1
1.2V
REF
Figure 3: Negative LDO Application Circuit
V
OUT
1
0
LDO
–
EN
–
ADJ
–
GND
BYP
–
C
BYP
–
C
ADJ
–
C
OUT
3260 F03
LTC3260
LDO
OUTPUT
R2
R1
–1.2V
REF
Negative Low Dropout Linear Regulator (LDO
–
)
The negative low dropout regulator (LDO
–
) supports a
load of up to 50mA. The LDO
–
takes power from the V
OUT
pin (output of the inverting charge pump) and drives the
LDO
–
output pin to a voltage programmed by the resis-
tor divider connected between the LDO
–
, ADJ
–
and GND
pins. For stability, the LDO
–
output must be bypassed to
ground with a low ESR ceramic capacitor that maintains a
capacitance of at least 2µF across operating temperature
and voltage.
The LDO
–
is enabled or disabled via the EN
–
logic input
pin. Initially, when the EN
–
logic input is low, the charge
pump circuitry is disabled and the V
OUT
pin is at GND.
When EN
–
is switched high, the V
OUT
pin will be driven