Datasheet

LTC3240-3.3/LTC3240-2.5
5
3240fb
Load Transient Response
(LTC3240-3.3)
Output Noise/Ripple
(LTC3240-2.5)
Load Transient Response
(LTC3240-2.5)
PI FU CTIO S
UUU
GND (Pin 1): Ground. This pin should be tied to a ground
plane for best performance.
V
IN
(Pin 2): Input Supply Voltage. V
IN
should be bypassed
with a 1μF or greater, low ESR ceramic capacitor.
V
OUT
(Pin 3): Regulated Output Voltage. V
OUT
should be
bypassed with a 4.7μF or greater, low ESR ceramic capaci-
tor as close to the pin as possible for best performance.
C
+
(Pin 4): Flying Capacitor Positive Terminal.
C
–
(Pin 5): Flying Capacitor Negative Terminal.
⎯
S
⎯
H
⎯
D
⎯
N (Pin 6): Active Low Shutdown Input. A low on
⎯
S
⎯
H
⎯
D
⎯
N
disables the LTC3240-3.3/LTC3240-2.5. This pin is a high
impedance CMOS input pin which must be driven with valid
logic levels. This pin must not be allowed to fl oat.
Exposed Pad (Pin 7): Ground. The exposed pad must be
soldered to PCB ground to provide electrical contact and
optimum thermal performance.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
(T
A
= 25°C, C
FLY
= C
IN
= 1µF, C
OUT
= 4.7µF
unless otherwise noted)
V
OUT
20mV/DIV
AC COUPLED
60mA
10mA
I
LOAD
10µs/DIV
3240 G15
V
IN
= 3.7V
I
LOAD
= 10mA TO 60mA
LDO MODE
V
OUT
20mV/DIV
AC COUPLED
500ns/DIV
3240 G16
V
IN
= 2.4V
I
LOAD
= 100mA
V
OUT
20mV/DIV
AC COUPLED
50mA
10mA
I
LOAD
10µs/DIV
3240 G17
V
IN
= 2.4V
I
LOAD
= 10mA TO 50mA
Burst Mode
OPERATION
CONST FREQUENCY
MODE