Datasheet

LTC3220/LTC3220-1
11
32201fc
Figure 3. Timing Parameters
ACK
123
ADDRESS WR
456789123456789123456789
00111 000
00111010
S7 S6 S5 S4 S3 S2 S1 S0
76543210
ACK
STOPSTART
SDA
SCL
ACK
ADDRESS
LTC3220-1
LTC3220 WR
00111000
S7 S6 S5 S4 S3 S2 S1 S0
76543210
SUB-ADDRESS
DATA BYTE
3220 FO2
Figure 2. Bit Assignments
t
SU, DAT
t
HD, STA
t
HD, DAT
SDA
SCL
t
SU, STA
t
HD, STA
t
SU, STO
3220 F03
t
BUF
t
LOW
t
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
r
t
f
t
SP
sub-address register is then written to, followed by the
data register. Each data register has a sub-address. After
the data register has been written a load pulse is created
after the stop bit. The load pulse transfers all of the data
held in the data registers to the DAC registers. The stop
bit can be delayed until all of the data master registers
have been written. At this point the LED current will be
changed to the new settings. The serial port uses static
logic registers so there is no minimum speed at which it
can be operated.
I
2
C Interface
The LTC3220/LTC3220-1 communicate with a host (master)
using the standard I
2
C 2-wire interface. The Timing Diagram
(Figure 3) shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus accelerator,
are required on these lines.
The LTC3220/LTC3220-1 are receive-only (slave) devices.
There are two I
2
C addresses available. The LTC3220 I
2
C
address is 0011100 and the LTC3220-1 I
2
C address is
0011101. The I
2
C address is the only difference between
the LTC3220 and LTC3220-1.
Write Word Protocol Used By the LTC3220/LTC3220-1
1711 81811
S Slave Address Wr A
*Sub-Address A Data Byte A P**
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge,
P = Stop Condition
*The sub-address uses only the fi rst 5 bits, D0, D1, D2, D3 and D4.
**Stop can be delayed until all of the data registers have been written.
OPERATION