Datasheet

LTC3219
11
3219fa
OPERATION
I
2
C Interface
The LTC3219 communicates with a host (master) using
the standard I
2
C 2-wire interface. The Timing Diagram
(Figure 2) shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus accelerator,
are required on these lines.
t
SU, DAT
t
HD, STA
t
HD, DAT
SDA
SCL
t
SU, STA
t
HD, STA
t
SU, STO
3219 F03
t
BUF
t
LOW
t
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
r
t
f
t
SP
Figure 3. Timing Parameters
ACK
123
ADDRESS WR
456789123456789123456789
00110 110
00110110
S7 S6 S5 S4 S3 S2 S1 S0
S7 S6 S5 S4 S3 S2 S1 S0
76543210
76543210
ACK
STOPSTART
SDA
SCL
ACK
SUB-ADDRESS
DATA BYTE
3219 FO2
Figure 2. Bit Assignments
The LTC3219 is a receive-only (slave) device.
Write Word Protocol Used by the LTC3219
1711 81811
S Slave Address Wr A
*Sub-Address A Data Byte A P**
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge,
P = Stop Condition
*The sub-address uses only the fi rst four bits, D0, D1, D2 and D3
**Stop can be delayed until all of the data registers have been written