Datasheet

LTC3217
10
3217fa
APPLICATIONS INFORMATION
and Y5V capacitors may also have a very poor voltage
coeffi cient causing them to lose 60% or more of their
capacitance when the rated voltage is applied. There-
fore, when comparing different capacitors, it is often
more appropriate to compare the amount of achievable
capacitance for a given case size rather than comparing
the specifi ed capacitance value. For example, over rated
voltage and temperature conditions, a 1μF, 10V, Y5V
ceramic capacitor in a 0603 case may not provide any
more capacitance than a 0.22μF, 10V, X7R available in
the same case. The capacitor manufacturer’s data sheet
should be consulted to determine what value of ca-
pacitor is needed to ensure minimum capacitances at all
temperatures and voltages.
Table 2 shows a list of ceramic capacitor manufacturers
and how to contact them:
Table 2. Recommended Capacitor Vendors
AVX www.avxcorp.com
Kemet www.kemet.com
Murata www.murata.com
Taiyo Yuden www.t-yuden.com
Vishay www.vishay.com
Layout Considerations and Noise
Due to its high switching frequency and the transient
currents produced by the LTC3217, careful board layout
is necessary. A true ground plane and short connections
to all capacitors will improve performance and ensure
proper regulation under all conditions.
The fl ying capacitor pins C1P, C2P, C1M and C2M will have
very high edge rate waveforms. The large dv/dt on these
pins can couple energy capacitively to adjacent PCB runs.
Magnetic fi elds can also be generated if the fl ying capacitors
are not close to the LTC3217 (i.e., the loop area is large).
To decouple capacitive energy transfer, a Faraday shield
may be used. This is a grounded PCB trace between the
sensitive node and the LTC3217 pins. For a high quality
AC ground, it should be returned to a solid ground plane
that extends all the way to the LTC3217.
The following guidelines should be followed when design-
ing a PCB layout for the LTC3217:
1. The Exposed Pad should be soldered to a large
copper plane that is connected to a solid, low imped-
ance ground plane using plated through-hole vias for
proper heat sinking and noise protection.
2. Input and output capacitors must be placed close to
the part.
3. The fl ying capacitors must be placed close to the
part. The traces from the pins to the capacitor pad
should be as wide as possible.
4. V
BAT
, CPO traces must be wide to minimize induc-
tance and handle high currents.
5. LED pads must be large and connected to other lay-
ers of metal to ensure proper LED heat sinking.
Power Effi ciency
To calculate the power effi ciency (η) of a white LED
driver chip, the LED power should be compared to the
input power. The difference between these two numbers
represents lost power whether it is in the charge pump
or the current sources. Stated mathematically, the power
effi ciency is given by:
η=
P
P
LED
IN
(5)
The effi ciency of the LTC3217 depends upon the mode in
which it is operating. Recall that the LTC3217 operates
as a pass switch, connecting V
BAT
to CPO, until dropout
is detected at the LED pin. This feature provides the op-
timum effi ciency available for a given input voltage and
LED forward voltage. When it is operating as a switch, the
effi ciency is approximated by:
η= = =
P
P
VI
VI
V
V
LED
IN
LED LED
BAT BAT
LED
BAT
(•)
(•)
(6)
since the input current will be very close to the sum of
the LED currents.