Datasheet

LTC3204-3.3/LTC3204-5/
LTC3204B-3.3/LTC3204B-5
11
3204fa
PACKAGE DESCRIPTIO
U
This can be achieved from a printed circuit board layout
with a solid ground plane and a good connection to the
ground pins of LTC3204-3.3/LTC3204-5/LTC3204B-3.3/
LTC3204B-5 and the exposed pad of the DFN package.
Figure 5. Maximum Power Dissipation
vs Ambient Temperature
Operation out of this curve will cause the junction tem-
perature to exceed 160°C which may trigger the thermal
shutdown.
AMBIENT TEMPERATURE (C)
POWER DISSIPATION (W)
3204 G05
3.0
2.5
2.0
1.5
1.0
0.5
0
–50
0
50
75
–25 25
100
125
150
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
2.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 ± 0.05
BOTTOM VIEW—EXPOSED PAD
0.56 ± 0.05
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
1.37 ±0.05
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DC6) DFN 1103
0.25 ± 0.05
1.42 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.61 ±0.05
(2 SIDES)
1.15 ±0.05
0.675 ±0.05
2.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
0.50 BSC
PIN
1
CHAMFER OF
EXPOSED PAD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
APPLICATIO S I FOR ATIO
W UU U