Datasheet

LTC3127
10
3127f
This causes poles and zeros to occur at the following
locations:
f
POLE2
@ DC
f
R C
f
R C
POLE
A
ZERO
A
3
2
1
2 2
1
2 1
=
• • •
=
• • •
π
π
The poles and zeros of the compensation should be deter-
mined by looking at where f
POLE1
lands at the minimum
load where the LTC3127 will be continuously conducting,
which places the dominant pole at its lowest frequency.
After setting the poles and zeros for the compensation, the
phase margin of the system should be greater than 45°
and the gain margin should be greater than 3dB. Following
these two criteria will help to ensure stability.
Current Limit Operation
The buck-boost converter has two current limit circuits.
The primary current limit is an average input current
limit circuit that clamps the output of the outer voltage
loop. This limits the amount of input current that can be
commanded, and the inner current loop regulates to that
clamped value.
operaTion
1.195V
SGND
PWM
C1
C2
R2
R1
R
A
LTC3127
V
OUT
C
OUT
V
C
V
OUT
FB
3127 F02
MEASURED
INPUT CURRENT
–
+
–
+
Figure 2. Buck-Boost External Compensation
Integral compensation is required if an output capacitor
less than 1000µF but greater than 44µF is used, otherwise
using proportional compensation is recommended.
When compensating the converter with integral compen-
sation it is important to consider that the total bandwidth
of the network must be below 15kHz. The inner current
loop of the LTC3127 eliminates one of the double poles
caused by the inductor. The output capacitor causes a
dominant pole and also a zero, and the resistor divider
sets the gain.
G
R
R
f
R C
f
DC
POLE
LOAD OUT
ZERO
= +
=
• • •
=
•
1
2
1
1
2
1
2
1
1
π
π
•• •R C
ESR OUT
Using the compensation network show in Figure 2, the
voltage loop compensation can be approximated with the
following transfer function:
H s
g C R s
s C C R s C C
COMP
m A
A
( )
( )
( )
=
• • • +
• • • • + +
1 1
1 2 1 2
where g
m
= 150 • 10
–6