Datasheet

LTC3114-1
25
Rev. C
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APPLICATIONS INFORMATION
verter for a transconductance gain of 1.97A/V. Similar to
peak current mode control, the inner average current mode
control loop effectively turns the inductor into a current
source over the frequency range of interest, resulting in a
frequency response from the power stage that exhibits a
single pole (–20dB/decade) roll off. The output capacitor
(C
OUT
) and load resistance (R
LOAD
) form the normally
dominant low frequency pole and the effective series
resistance of the output capacitor and its capacitance form
a zero, usually at a high enough frequency to be ignored. A
potentially troublesome right half plane zero (RHPZ) is also
encountered if the LTC3114-1 is operated in boost mode.
The RHPZ causes an increase in gain, like a zero, but a
decrease in phase, like a pole. This will ultimately limit the
maximum converter bandwidth that can be achieved with
the LTC3114-1. The RHPZ is not present when operating
in buck mode. The overall open loop gain at DC is the
product of the following terms:
Voltage Error Amp Gain:
g
m
• R
O
= 120µs • 3.6M = 432V/V (not adjustable)
Voltage Divider Gain:
V
FB
V
OUT
=
1V
V
OUT
(determined by the application, V
FB
is the reference
voltage for the voltage error amplifier)
Current Loop Transconductance:
G
C
=
1.7A
0.865V
= 1.97A/V
(not adjustable)
Load Resistance (R
LOAD
) (determined by the application)
The frequency dependent terms that affect the loop gain
include:
Output Load Pole(P1):
1
2π •R
LOAD
•C
OUT
(application dependent)
Error Amplifier Compensation (2 Poles and 1 Zero):
These are the design variables available
Right Half Plane Zero (RHPZ): boost mode only (de
-
termined by maximum load, V
IN
, V
OUT
and inductor)
Current Amplifier Compensation Components (Fixed
Internal to the LTC3114-1)
The internal current amplifier and inner current loop
have a much higher bandwidth than the overall loop,
however, unlike an ideal V
CCS
with a flat gain versus
frequency characteristic, the inner loop exhibits gain
peaking in the range of approximately 2kHz to 20kHz
that is an artifact of the fixed current amplifier compen
-
sation. This gain peaking has the effect of pushing out
the overall loop crossover frequency
, while
providing some phase margin boost as well. As long as
there is sufficient margin between the loop crossover
frequency and the worst-case RHPZ frequency, then
stable operation over all conditions is relatively easy
to achieve.
The design parameters for compensation design will focus
on the series resistor and capacitors connected from VC to
ground (R
Z
, C
P1
and C
P2
). The general goal is to provide
a phase boost using the compensation network zero in
order to maximize the bandwidth and phase margin of the
converter. Being a buck-boost converter, the target loop
crossover frequency for the compensation design will be
dictated by the highest boost ratio and load current that is
expected as this will result in the lowest RHPZ frequency.
An illustrative example is provided next that will derive
the compensation components for a typical LTC3114-1
application.
Compensation Example
This section will demonstrate how to derive and select
the compensation components for a typical LTC3114-1
application. Designing compensation for other applications
+
–
g
m
1V
1V
g
m
= 1.7A/0.865V
+
–
FB
VOLTAGE
ERROR
AMP
VOLTAGE
CONTROLLED
CURRENT
SOURCE
VC
GND
R
Z
R
TOP
1.7M
R
BOT
100k
R
COSER
0.01Ω
R
LOAD
18Ω
C
P1
C
OUT
22µF
V
OUT
C
P2
31141 F06
Figure6. Simplified Representation of
Average Current Mode Control Loop
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