Datasheet

LTC3109
4
3109fb
For more information www.linear.com/LTC3109
Typical perForMance characTerisTics
elecTrical characTerisTics
board layout, the rated thermal package thermal resistance and other
environmental factors. The junction temperature (T
J
) is calculated from
the ambient temperature (T
A
) and power dissipation (P
D
) according to
the formula: T
J
= T
A
+ (P
D
• θ
JA
°C/W), where θ
JA
is the package thermal
impedance.
Note 3: Specification is guaranteed by design and not 100% tested in
production.
Note 4: Current measurements are made when the output is not switching.
Note 5: Failure to solder the exposed backside of the QFN package to the
PC board ground plane will result in a thermal resistance much higher
than 37°C/W.
Note 6: The Absolute Maximum Rating is a DC rating. Under certain
conditions in the applications shown, the peak AC voltage on the C2A and
C2B pins may exceed ±8V. This behavior is normal and acceptable because
the current into the pin is limited by the impedance of the coupling
capacitor.
Input Resistance vs V
IN
Efficiency vs V
IN
Open-Circuit Start-Up Voltage
vs Source Resistance
I
IN
vs V
IN
I
VOUT
vs V
IN
V
IN
(mV)
10
1
I
IN
(mA)
10
100
1000
100 1000
3109 G01
1:100 RATIO, C1 = 1nF
1:50 RATIO, C1 = 4.7nF
1:20 RATIO, C1 = 10nF
V
OUT
= 0V
V
IN
(mV)
10
10
I
VOUT
(µA)
100
1000
10000
100 1000
3109 G02
1:100 RATIO, C1 = 1nF
1:50 RATIO, C1 = 4.7nF
1:20 RATIO, C1 = 10nF
V
OUT
= 3.3V
NO LOAD ON VLDO
V
IN
(mV)
10
2.0
R
IN
(Ω)
3.0
4.0
5.0
6.0
100 1000
3109 G03
7.0
2.5
3.5
4.5
5.5
6.5
1:100 RATIO, C1 = 1nF
1:50 RATIO, C1 = 4.7nF
1:20 RATIO, C1 = 10nF
V
OUT
= 0V
SOURCE RESISTANCE (Ω)
0
0
V
STARTUP
(OPEN CIRCUIT) (mV)
10
30
40
50
6 7 8 9
90
3109 G05
20
1 2 3 4 5 10
60
70
80
V
IN
(mV)
10
0
EFFICIENCY (%)
10
20
30
40
100 1000
3109 G04
50
5
15
25
35
45
1:100 RATIO, C1 = 1nF
1:50 RATIO, C1 = 4.7nF
1:20 RATIO, C1 = 10nF
V
OUT
= 0V
T
A
= 25°C, unless otherwise noted.
V
IN
(mV)
10
0.1
P
VOUT
(mW)
1
10
100
100 1000
3109 G18
1:50 RATIO
C1 = 4.7nF
V
OUT
= 5V
V
OUT
= 3.3V
P
VOUT
vs V
IN