Datasheet

LTC3108
16
3108fc
For more information www.linear.com/LTC3108
The VSTORE capacitor may be of very large value (thou-
sands of microfarads or even Farads), to provide holdup
at times when the input power may be lost. Note that this
capacitor can charge all the way to 5.25V (regardless of
the settings for V
OUT
), so ensure that the holdup capacitor
has a working voltage rating of at least 5.5V at the tem
-
perature for which it will be used. The VSTORE capacitor
can be sized using the following:
[]
≥
++ +
−
C
6µAI I(I•t•f) •TSTORE
5.25 V
STORE
QLDO BURST
OUT
Where 6µA is the quiescent current of the LTC3108, I
Q
is
the load on V
OUT
in between bursts, I
LDO
is the load on the
LDO between bursts, I
BURST
is the total load during the
burst, t is the duration of the burst, f is the frequency of
the bursts, TSTORE is the storage time required and V
OUT
is the output voltage required. Note that for a programmed
output voltage of 5V, the VSTORE capacitor cannot provide
any beneficial storage time.
To minimize losses and capacitor charge time, all capaci
-
tors used for V
OUT
and VSTORE should be low leakage.
See Table 6 for recommended storage capacitors.
Table 6. Recommended Storage Capacitors
VENDOR PART NUMBER/SERIES
AVX
www.avx.com
BestCap Series
TAJ and TPS Series Tantalum
Cap-XX
www.cap-xx.com
GZ Series
Cooper/Bussmann
www.bussmann.com/3/PowerStor.html
KR Series
P Series
Vishay/Sprague
www.vishay.com/capacitors
Tantamount 592D
595D Tantalum
150CRZ/153CRV Aluminum
013 RLC (Low Leakage)
Storage capacitors requiring voltage balancing are not
recommended due to the current draw of the balancing
resistors.
PCB Layout Guidelines
Due to the rather low switching frequency of the resonant
converter and the low power levels involved, PCB layout
is not as critical as with many other DC/DC converters.
There are, however, a number of things to consider.
Due to the very low input voltage the circuit may operate
from, the connections to V
IN
, the primary of the trans-
former and the SW and GND pins of the LTC3108 should
be designed to minimize voltage drop from stray resistance
and able to carry currents as high as 500mA. Any small
voltage drop in the primary winding conduction path will
lower efficiency and increase capacitor charge time.
Also, due to the low charge currents available at the out
-
puts of the LTC3108, any sources of leakage current on
the output voltage pins must be minimized. An example
board layout is shown in Figure 3.
applicaTions inForMaTion
3108 FO3
V
OUT2
V
OUT
V
IN
VIAS TO GROUND PLANE
VLDO
PGOOD
GND
12
11
8
9
10
4
5
3
2
1
V
OUT2_EN
VS1
VS2
SW
C2
C1
V
OUT
V
OUT2
VLDO
PGD
VAUX
VSTORE
6
7
Figure 3. Example Component Placement
for Two-Layer PC Board (DFN Package)
Design Example 1
This design example will explain how to calculate the
necessary storage capacitor value for V
OUT
in pulsed load
applications, such as a wireless sensor/transmitter. In these
types of applications, the load is very small for a major
-
ity of the time (while the circuitry is in a low power sleep
state), with bursts of load current occurring periodically
during a transmit burst. The storage capacitor on V
OUT
supports the load during the transmit burst, and the long
sleep time between bursts allows the LTC3108 to recharge
the capacitor. A method for calculating the maximum rate