Datasheet

LTC3101
17
3101fb
OPERATION
Low Dropout Operation
As the input voltage decreases to a value approaching
the output regulation voltage, the duty cycle increases to
the maximum on-time of the P-channel switch. Further
reduction of the supply voltage will force the main switch
to remain on for more than one cycle and subharmonic
switching will occur to provide a higher effective duty cycle.
If the input voltage is decreased further, the buck converter
will enter 100% duty cycle operation and the P-channel
switch will remain on continuously. In this dropout state,
the output voltage is determined by the input voltage less
the resistive voltage drop across the P-channel switch and
series resistance of the inductor.
Slope Compensation
Current mode control requires the use of slope compensa-
tion to prevent sub-harmonic oscillations in the inductor
current waveform at high duty cycle operation. This function
is performed internally on the LTC3101 through the addition
of a compensating ramp to the current sense signal. In
some current mode ICs, current limiting is performed by
clamping the error amplifi er voltage to a fi xed maximum.
This leads to a reduced output current capability at low
step-down ratios. In contrast, the LTC3101 performs cur-
rent-limiting prior to addition of the slope compensation
ramp and therefore achieves a peak inductor current limit
that is independent of duty cycle.
Output Short-Circuit Operation
When the output is shorted to ground, the error amplifi er
will saturate high and the P-channel switch will turn on
at the start of each cycle and remain on until the current
limit trips. During this minimum on-time of the P-channel
switch, the inductor current will increase rapidly but will
decrease very slowly during the remainder of the period
due to the very small reverse voltage produced by a hard
output short. To eliminate the possibility of inductor current
runaway in this situation, the switching frequency of the
buck converters is reduced by a factor of four when the
voltage on the respective feedback pin (FB1 or FB2) falls
below 0.3V. This provides additional time for the inductor
current to reset and thereby protects against a build-up
of current in the inductor.
Internal Voltage Mode Soft-Start
Each buck converter has an independent internal voltage
mode soft-start circuit with a nominal duration of 800s.
The buck converters remain in regulation during soft-start
and will therefore respond to output load transients which
occur during this time. In addition, the output voltage rise-
time has minimal dependency on the size of the output
capacitor or load current during start-up.
Error Amplifi er and Internal Compensation
The LTC3101 buck converters utilize internal transconduc-
tance error amplifi ers. Compensation of the buck converter
feedback loops is performed internally to reduce the size
of the application circuit and simplify the design process.
The compensation network has been designed to allow use
of a wide range of output capacitors while simultaneously
ensuring a rapid response to load transients.
Power Good Comparator Operation
Each buck converter has an internal power good compara-
tor that monitors the respective feedback pin voltage (FB1
or FB2). The power good comparator outputs are used at
power-up for sequencing purposes. During normal opera-
tion, the power good comparators are used to monitor
the output rails for a fault condition. If either buck power
good comparator indicates a fault condition, the C
RS
and
RESET pins are driven low. This can be used to reset a
microprocessor in the application circuit when either buck
converter output rail loses regulation.
The buck power good comparator will trip when the
respective feedback pin falls 8% (nominally) below the
regulation voltage. With a rising output voltage, the power
good comparator will typically clear when the respective
feedback voltage rises to within 5.5% of the regulation
voltage. In addition, there is a 60s typical deglitching
delay in the power good comparators in order to prevent
false trips due to brief voltage transients occurring on
load steps.