Datasheet

LTC3025
7
3025fd
using the formula in Figure 2. Note that in shutdown the
output is turned off and the divider current will be zero
once C
OUT
is discharged.
The LTC3025 operates at a relatively high gain of –0.7µV/
mA referred to the ADJ input. Thus a load current change
of 1mA to 300mA produces a –0.2mV drop at the ADJ
input. To calculate the change referred to the output sim-
ply multiply by the gain of the feedback network (i. e. ,1
+ R2/R1). For example, to program the output for 1.2V
choose R2/R1 = 2. In this example, an output current
change of 1mA to 300mA produces –0.2mV • (1 + 2) =
0.6mV drop at the output.
Because the ADJ pin is relatively high impedance (depend-
ing on the resistor divider used) , stray capacitance at this
pin should be minimized (<10pF) to prevent phase shift
in the error amplifi er loop. Additionally, special attention
should be given to any stray capacitances that can couple
external signals onto the ADJ pin producing undesirable
output ripple. For optimum performance connect the ADJ
pin to R1 and R2 with a short PCB trace and minimize all
other stray capacitance to the ADJ pin.
()
OUT
R1
R2
3025 F02
C
OUT
R2
R1
V
OUT
= 0.4V 1 
ADJ
GND
Figure 2. Programming the LTC3025
APPLICATIONS INFORMATION
Output Capacitance and Transient Response
The LTC3025 is designed to be stable with a wide range of
ceramic output capacitors. The ESR of the output capaci-
tor affects stability, most notably with small capacitors. A
minimum output capacitor of 1µF with an ESR of 0.05Ω
or less is recommended to ensure stability. The LTC3025
is a micropower device and output transient response
will be a function of output capacitance. Larger values
of output capacitance decrease the peak deviations and
provide improved transient response for larger load current
changes. Note that bypass capacitors used to decouple
individual components powered by the LTC3025 will
increase the effective output capacitor value. High ESR
tantalum and electrolytic capacitors may be used, but
a low ESR ceramic capacitor must be in parallel at the
output. There is no minimum ESR or maximum capacitor
size requirements.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common di-
electrics used are Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but exhibit large voltage and tem-
perature coeffi cients as shown in Figures 3 and 4. When
used with a 2V regulator, a 1µF Y5V capacitor can lose as
much as 75% of its initial capacitance over the operating
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3025 F03
20
0
–20
–40
–60
–80
–100
0
4
8
10
26
X5R
Y5V
BOTH CAPACITORS ARE 1µF,
10V, 0603 CASE SIZE
Figure 3. Ceramic Capacitor DC Bias Characteristics
TEMPERATURE (°C)
–50
–100
CHANGE IN VALUE (%)
–80
–60
–40
–20
X5R
Y5V
20
–25
02550
3025 F04
75
0
BOTH CAPACITORS ARE 1µF,
10V, 0603 CASE SIZE
Figure 4. Ceramic Capacitor Temperature Characteristics