Datasheet

LTC2991
16
2991fd
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applicaTions inForMaTion
slave is the receiver, it must pull down the SDA line so that
it remains LOW during this pulse to acknowledge receipt
of the data. If the slave fails to acknowledge by leaving
SDA HIGH, then the master can abort the transmission by
generating a STOP condition. After the master has received
the last data bit from the slave, the master must pull down
the SDA line during the next clock pulse to indicate receipt
of the data. After the last byte has been received the master
will leave the SDA line HIGH (not acknowledge) and issue
a STOP condition to terminate the transmission.
Write Protocol
The master begins communication with a START condition
followed by the 7-bit slave address and the RW bit set to
zero. The addressed LTC2991 acknowledges the address
and then the master sends a command byte which indi-
cates which internal register the master wishes to write.
The LTC2991 acknowledges the command byte and then
latches the lower five bits of the command byte into its
internal register address pointer. The master then deliv-
ers the data byte and the LTC2991 acknowledges once
more and latches the data into its internal register. The
transmission is ended when the master sends a STOP
condition. If the master continues sending a second data
byte, as in a write word command, the second data byte
will be acknowledged by the LTC2991 and written to the
next register in sequence, if this register has write access.
Read Protocol
The master begins a read operation with a START condition
followed by the 7-bit slave address and the RW bit set to
zero. The addressed LTC2991 acknowledges this and then
the master sends a command byte which indicates which
internal register the master wishes to read. The LTC2991
acknowledges this and then latches the lower five bits
of the command byte into its internal register address
pointer. The master then sends a repeated START condi-
tion followed by the same seven bit address with the RW
bit now set to one. The LTC2991 acknowledges and sends
the contents of the requested register. The transmission
is ended when the master sends a STOP condition. The
register pointer is automatically incremented after each
byte is read. If the master acknowledges the transmitted
data byte, as in a read word command, the LTC2991 will
send the contents of the next sequential register as the
second data byte. The byte following register 1Fh is register
0h, or the status register.
Control Registers
The control registers (Tables 5 through 8) determine the
selected measurement mode of the device. The LTC2991 can
be configured to measure voltages, currents and tempera-
tures. These measurements can be single shot or repeated
measurements. Temperatures can be set to report in Celsius
or Kelvin temperature scales. The LTC2991 can be configured
to run particular measurements, or all possible measure-
ments per the configuration specified by the channel enable
register (Table 4). The power-on default configuration of the
control registers is 00h, which translates to a single-ended
voltage measurement of the triggered channels. This mode
prevents the application of remote diode test currents on
pins V1, V3, V5 and V7, and remote diode terminations on
pins V2, V4, V6 and V8 at power-up.
Status Register
The status registers (Tables 3 and 4) report the status of a
particular conversion result. When new data is written into
a particular result register, the corresponding DATA_VALID
bit is set. When the register is addressed by the I
2
C inter-
face, the status bit (as well as the DATA_VALID bit in the
respective register) is cleared. The host can then determine
if the current available register data is new or stale. The
busy bit, when high, indicates a single shot conversion is
in progress. The busy bit is always high during repeated
mode, after the initial conversion is triggered.
Figure 4. Data Transfer Over I
2
C or SMBus
STOP
2991 F04
START ADDRESS R/W
P
981-71-71-7
a6-a0 b7-b0 b7-b0
9898
S
DATA DATAACK ACK ACK