Datasheet

LTC2991
15
2991fd
For more information www.linear.com/LTC2991
applicaTions inForMaTion
the PWM Threshold, the PWM output pin will be a constant
logic level 1. This relationship is opposite if the PWM
invert bit is set. If the filter is enabled for the V7/V8 pair,
the filtered result is routed to the PWM block; otherwise,
the unfiltered version is used. The PWM CMOS output
drive is intended to be buffered to drive large (>100pF)
external capacitances or resistors <10k. A recommended
noninverting buffer is a NC7SZ125 to increase the drive
capability of the PWM signal.
Digital Filter
Each conversion result can be filtered using an on-chip
digital filter. The filter equation is:
OUTPUT[X] = (15 • (OUTPUT[X – 1]) + SAMPLE[X])/16
where output[x] is the register value when enabled. The
filter step response is illustrated in the Typical Perfor
-
mance Characteristics section. The filter can be seeded
by triggering an unfiltered conversion of each configured
measurement, then subsequently enabling the filter. This
will cause the filter to converge instantaneously to the value
of the initial unfiltered sample. The filter can be enabled
or disabled for each channel pair and internal temperature
measurements. V
CC
measurements cannot be filtered.
Digital Interface
The LTC2991 communicates with a bus master using
a 2-wire interface compatible with the I
2
C Bus and the
SMBus, an I
2
C extension for low power devices.
The LTC2991 is a read write slave device and supports
SMBus bus read byte data and write byte data, read word
data and write word data commands. The data formats
for these commands are shown in Tables 3 though 15.
The connected devices can only pull the bus wires LOW
and can never drive the bus HIGH. The bus wires are
externally connected to a positive supply voltage via a
current source or pull-up resistor. When the bus is free,
both lines are HIGH. Data on the I
2
C bus can be transferred
at rates of up to 100kbit/s in the standard mode and up to
400kbit/s in the fast mode. Each device on the I
2
C bus is
recognized by a unique address stored in that device and
can operate as either a transmitter or receiver, depending
on the function of the device. In addition to transmitters
and receivers, devices can also be considered as masters
or slaves when performing data transfers. A master is
the device which initiates a data transfer on the bus and
generates the clock signals to permit that transfer. At the
same time any device addressed is considered a slave.
The LTC2991 can only be addressed as a slave. Once ad-
dressed, it can receive configuration bits or transmit the
last conversion result. Therefore the serial clock line SCL
is an input only and the data line SDA is bidirectional. The
device supports the standard mode and the fast mode for
data
transfer speeds up to 400kbit/s. The Timing Diagram
shows the definition of timing for fast/standard mode
devices on the I
2
C bus. The internal state machine cannot
update internal data registers during an I
2
C read operation.
The state machine pauses until the I
2
C read is complete.
It is therefore, important not to leave the LTC2991 in this
state for long durations, or increased conversion latency
will be experienced.
START and STOP Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with
a START condition by transitioning SDA from high to low
while SCL is high. When the bus is in use, it stays busy
if a repeated START (SR) is generated instead of a STOP
condition. The repeated START (SR) conditions are func-
tionally identical to the START (S). When the master has
finished communicating with the slave, it issues a STOP
condition by transitioning SDA from low to high while SCL
is high. The bus is then free for another transmission.
I
2
C Device Addressing
Eight distinct bus addresses are configurable using the
ADR0, ADR1 and ADR2 pins. Table 1 shows the corre-
spondence between ADR0, ADR1 and ADR2 pin states and
addresses. There is also one global sync address available
at EEh which provides an easy way to synchronize multiple
LTC2991’s on the same I
2
C bus. This allows write only access
to all LTC2991’s on the bus for simultaneous triggering.
Acknowledge
The acknowledge signal is used for handshaking between
the transmitter and the receiver to indicate that the last byte
of data was received. The transmitter always releases the
SDA line during the acknowledge clock pulse. When the