Datasheet

LTC2978A
70
2978afa
For more information www.linear.com/LTC2978A
APPLICATIONS INFORMATION
• PWRGD reflects the status of the outputs that are mapped
to it by the MFR_PWRGD_EN command. Figure 20
shows all the PWRGD pins connected together, but any
combination may be used. Note that the latency of the
PWRGD pin response may be in the range of 30ms to
185ms depending on ADC MUX settings. See Electrical
Characteristics Table Note 4.
A fast deassertion of PWRGD may be implemented by
wire ANDing the V
IN_EN
pin with the PWRGD pin. If, for
example, a UV or OV fault threshold is crossed, V
IN_EN
will pull low if the associated bit in the MFR_VINEN_UV_
FAULT_RESPONSE or MFR_VINEN_OV_FAULT_RE
-
SPONSE register is set. See Figure 22.
APPLICATION CIRCUITS
Trimming and Margining DC/DC Converters with
External Feedback Resistors
Figure 23 shows a typical application circuit for trimming/
margining a power supply with an external feedback
network. The V
SENSEP0
and V
SENSEM0
differential inputs
sense the load voltage directly, and a correction voltage
is developed between the V
DACP0
and V
DACM0
pins
by the closed-loop servo algorithm. V
DACM0
is Kelvin
connected to the point-of-load GND in order to minimize
the effects
of load induced grounding errors. The V
DACP0
output is connected to the DC/DC converter’s feedback
node through resistor R30. For this configuration, set
Mfr_config_dac_pol to 0.
Figure 21. Aborted On Sequence Due to Channel 1 Short
Figure 22. PWRGD Deassert
V
CONTROLn
V
OUT0
TON_DELAY0
V
OUT1
V
OUT2
V
OUTn
BUSSED
VFAULTBz
n
PINS
TON_MAX_FAULT1
2978a F21
TON_DELAY1
TON_DELAY2
TON_DELAYn
•
•
•
•
•
•
LTC2978A
V
IN_EN
V
DD33
FAST PWRGD
DEASSERT
PWRGD
4.7k
2978a F22
VIN_EN/PWRGD
VOUTn UV FAULT LIMIT
t
S_VS