Datasheet

LTC2978A
20
2978afa
For more information www.linear.com/LTC2978A
chip will respond by beginning a soft-start sequence. In
this case the slowest VIN_ON detection will take over and
synchronize other chips to its soft-start sequence.
PMBus SERIAL DIGITAL INTERFACE
The LTC2978A communicates with a host (master) using
the standard PMBus serial bus interface. The PMBus Timing
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
The LTC2978A is a slave device. The master can com
-
municate with
the LTC2978A using the following formats:
n
Master transmitter, slave receiver
n
Master receiver, slave transmitter
The following SMBus protocols are supported:
n
Write Byte, Write Word, Send Byte
n
Read Byte, Read Word, Block Read
n
Alert Response Address
Figures 1-12 illustrate the aforementioned SMBus
protocols. All transactions support PEC (parity error check)
and GCP (group command protocol). The Block Read
supports 255 bytes of returned data. For this reason, the
PMBus timeout may be extended using the Mfr_config_all_
longer_pmbus_timeout setting.
The LTC2978A will not acknowledge any PMBus command
if it is
still busy with a STORE_USER_ALL, RESTORE_
USER_ALL,
MFR_CONFIG_LTC2978 or if fault log data
is being written to the EEPROM. Status_word_busy will
also be set, but ALERTB will not be asserted low.
PMBus
PMBus is an industry standard that defines a means
of communication with power conversion devices. It is
comprised of an industry standard SMBus serial interface
and the PMBus command language.
The PMBus two wire interface is an incremental extension
of the SMBus. SMBus is built upon I
2
C with some minor
differences in timing, DC parameters and protocol. The
SMBus protocols are more robust than simple I
2
C byte
commands because they provide timeouts to prevent
bus hangs and optional packet error checking (PEC) to
ensure data integrity. In general, a master device that
can be configured for I
2
C communication can be used
for PMBus communication with little or no change to
hardware or firmware.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.1: paragraph 5: Transport. This can be
found at:
www.pmbus.org.
For a description of the differences between SMBus and
I
2
C, refer to system management bus (SMBus) specifica-
tion version 2.0:
Appendix B – Differences Between SMBus
and I
2
C. This can be found at:
www.smbus.org.
When using an I
2
C controller to communicate with a
PMBus part it is important that the controller be able to
write
a byte of data without generating a stop. This will
allow the controller to properly form the repeated start
of the PMBus read command by concatenating a start
command byte write with an I
2
C read.
OPERATION