Datasheet

LTC2974
9
2974fc
For more information www.linear.com/LTC2974
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
J
= 25°C. V
PWR
= V
IN_SNS
= 12V, V
DD33
, V
DD25
, REFP and REFM pins floating,
unless otherwise indicated. C
VDD33
= 100nF, C
VDD25
= 100nF and C
REF
= 100nF.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified. If power is supplied to the chip via the V
DD33
pin only, connect
V
PWR
and V
DD33
pins together.
Note 3: Hysteresis in the output voltage is created by package stress
that differs depending on whether IC was previously at a higher or lower
temperature. Output voltage is always measured at 25°C, but the IC is
cycled to 85°C or –40°C before successive measurements. Hysteresis is
roughly proportional to the square of the temperature change.
Note 4: The current sense resolution is determined by the L11 format and
the mV units of the returned value. For example, a full-scale value of 170mV
returns a L11 value of 0xF2A8 = 680 • 2
–2
= 170. This is the lowest range
that can represent this value without overflowing the L11 mantissa and
the resolution for 1LSB in this range is 2
–2
mA = 250µA. Each successively
lower range improves resolution by cutting the LSB size in half.
Note 5: The nominal time between successive ADC conversions (latency of
the ADC) for any given channel is t
UPDATE_ADC
.
Note 6: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to full-scale code, 1023.
Note 7: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 8: The LTC2974 will not acknowledge any PMBus commands,
except for MFR_COMMON, when a STORE_USER_ALL command is being
executed. See also OPERATION section.
Note 9: Maximum capacitive load, C
B
, for SCL and SDA is 400pF. Data and
clock risetime (t
r
) and falltime (t
f
) are: (20 + 0.1• C
B
) (ns) < t
r
< 300ns and
(20 + 0.1 • C
B
) (ns) < t
f
< 300ns. C
B
= capacitance of one bus line in pF.
SCL and SDA external pull-up voltage, V
IO
, is 3.13V < V
IO
< 3.6V.
elecTrical characTerisTics
pMbus TiMing DiagraM
SDA
SCL
t
HD(STA)
t
HD(DAT)
t
SU(STA)
t
SU(STO)
t
SU(DAT)
t
LOW
t
HD(STA)
t
SP
t
BUF
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
t
r
t
f
t
r
t
f
t
HIGH
2974 TD
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
SU,STO
Stop Condition Setup Time (Note 9)
l
600 ns
t
HD,DAT
Data Hold Time (LTC2974 Receiving
Data) (Note 9)
l
0 ns
Data Hold Time (LTC2974 Transmitting
Data) (Note 9)
l
300 900 ns
t
SU,DAT
Data Setup Time (Note 9)
l
100 ns
t
SP
Pulse Width of Spike Suppressed
(Note 9)
98 ns
t
TIMEOUT_BUS
Time Allowed to Complete any PMBus
Command After Which Time SDA Will
Be Released and Command Terminated
Longer Timeout = 0
Longer Timeout = 1
l
l
25
200
35
280
ms
ms
Additional Digital Timing Characteristics
t
OFF_MIN
Minimum Off Time for Any Channel 100 ms