Datasheet

LTC2974

2974fc

For more information www.linear.com/LTC2974

pMbus coMManD DescripTion

b[1] Mfr_pwrgd_en_chan1 Channel 1.

1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when

the PWRGD pin gets asserted.

0 = PWRGD status for this channel does not affect the PWRGD pin.

b[0] Mfr_pwrgd_en_chan0 Channel 0.

1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when

the PWRGD pin gets asserted.

0 = PWRGD status for this channel does not affect the PWRGD pin.

MFR_POWERGOOD_ASSERTION_DELAY

This command register allows the user to program the delay from when the internal power-good signal becomes valid

until the power-good output is asserted. This delay is counted using SHARE_CLK if available, otherwise the internal

oscillator is used. This delay is internally limited to 13.1 seconds, and rounded to the nearest 200µs. The read value

of this command always returns what was last written and does not reflect internal limiting.

The power good de-assertion delay and threshold source is controlled by Mfr_config_all_pwrgd_off_uses_uv. Sys

tems that require a fast power good de-assertion should set Mfr_config_all_pwrgd_off_uses_uv=1. This uses the

VOUT_UV_FAULT_LIMIT and the high speed comparator to de-assert the PWRGD pin. Systems that require a separate

power good off threshold should set Mfr_config_all_pwrgd_off_uses_uv=0. This uses the slower ADC polling loop

and POWER_GOOD_OFF to de-assert the PWRGD pin.

Watchdog Operation

A non-zero write to the MFR_WATCHDOG_T register will reset the watchdog timer. Low-to-high transitions on the

WDI/RESETB pin also reset the watchdog timer. If the timer expires, ALERTB is asserted and the PWRGD output

is optionally de-asserted and then reasserted after MFR_PWRGD_ASSERTION_DELAY ms. Writing 0 to either the

MFR_WATCH_DOG_T or MFR_WATCHDOG_T_FIRST registers will disable the timer.

MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T

The MFR_WATCHDOG_T_FIRST register allows the user to program the duration of the first watchdog timer interval

following assertion of the PWRGD pin, assuming the PWRGD pin reflects the status of the watchdog timer. If asser

tion of PWRGD is not conditioned by the watchdog timer’s status, then MFR_WATCHDOG_T_FIRST applies to the first

timing interval after the timer is enabled. Writing a value of 0ms to the MFR_WATCHDOG_T_FIRST register disables

the watchdog timer. This delay is internally limited to 65 seconds and rounded to the nearest 1ms.

The MFR_WATCHDOG_T register allows the user to program watchdog timer intervals subsequent to the MFR_WATCH

DOG_T_FIRST timing interval. Writing a value of 0ms to the MFR_WATCHDOG_T register disables the watchdog timer.

This delay is internally limited to 655ms and rounded to the nearest 10µs.

Both timers operate on an internal clock independent of SHARE_CLK. The read value of both commands always returns

what was last written and does not reflect internal limiting.