Datasheet

LTC2974
52
2974fc
For more information www.linear.com/LTC2974
Clock Sharing
Multiple LTC PMBus devices can synchronize their clocks in an application by connecting together the open-drain
SHARE_CLK input/outputs to a pull-up resistor as a wired OR. In this case the fastest clock will take over and syn
-
chronize all other chips to its falling edge.
SHARE_CLK can optionally be used to synchronize ON/OFF dependency on V
IN
across multiple chips by setting the
Mfr_config_all_vin_share_enable bit of the MFR_CONFIG_ALL register. When configured this way the chip will hold
SHARE_CLK low when the unit is off for insufficient input voltage, and upon detecting that SHARE_CLK is held low
the chip will disable all channels after a brief deglitch period. When the SHARE_CLK pin is allowed to rise, the chip
will respond by beginning a start sequence. In this case the slowest VIN_ON detection will take over and synchronize
other chips to its start sequence.
pMbus coMManD DescripTion
WATCHDOG TIMER AND POWER GOOD
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED FORMAT UNITS EEPROM
DEFAULT
VALUE
REF
PAGE
MFR_PWRGD_EN 0xD4 Configuration that maps WDI/
RESETB status and individual
channel power good to the
PWRGD pin.
R/W Word N Reg Y 0x0000
52
MFR_POWERGOOD_ASSERTION_DELAY 0xE1 Power-good output assertion
delay.
R/W Word N L11 ms Y 100
0xEB20
53
MFR_WATCHDOG_T_FIRST 0xE2 First watchdog timer interval. R/W Word N L11 ms Y 0
0x8000
53
MFR_WATCHDOG_T 0xE3 Watchdog timer interval. R/W Word N L11 ms Y 0
0x8000
53
MFR_PWRGD_EN
This command register controls the mapping of the watchdog and channel power good status to the PWRGD pin.
MFR_PWRGD_EN Data Contents
BIT(S) SYMBOL OPERATION
b[15:9] Reserved Read only, always returns 0s.
b[8] Mfr_pwrgd_en_wdog Watchdog.
1 = Watchdog timer not-expired status is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = Watchdog timer does not affect the PWRGD pin.
b[7:4] Reserved Always returns 0000b.
b[3] Mfr_pwrgd_en_chan3 Channel 3.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
b[2] Mfr_pwrgd_en_chan2 Channel 2.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.