Datasheet

LTC2974
18
2974fc
For more information www.linear.com/LTC2974
operaTion
RESETB
Holding the WDI/RESETB pin low for more than t
RESETB
will cause the LTC2974 to enter the power-on reset state.
While in the power-on reset state, the device will not
communicate on the I
2
C bus. Following the subsequent
rising-edge of the WDI/RESETB pin, the LTC2974 will
execute its power-on sequence per the user configuration
stored in EEPROM. Connect WDI/RESETB to VDD33 with
a 10k resistor. WDI/RESETB includes an internal 256μs
deglitch filter so additional filter capacitance on this pin
is not recommended.
PMBus SERIAL DIGITAL INTERFACE
The LTC2974 communicates with a host (master) using the
standard PMBus serial bus interface. The PMBus Timing
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
The LTC2974 is a slave device. The master can communicate
with the LTC2974 using the following formats:
• Master transmitter, slave receiver
• Master receiver, slave transmitter
The following SMBus commands are supported:
• Write Byte, Write Word, Send Byte
• Read Byte, Read Word, Block Read
• Alert Response Address
Figures 1 to 12 illustrate the aforementioned SMBus proto
-
cols. All transactions support PEC (parity error check) and
GCP (group command protocol). The Block Read supports
255 bytes of returned data. For this reason, the SMBus
timeout may be extended using the Mfr_config_all_lon
-
ger_pmbus_timeout setting.
PMBus
PMBus is an industry standard that defines a means
of communication with power conversion devices. It is
comprised of an industry standard SMBus serial interface
and the PMBus command language.
The PMBus two wire interface is an incremental extension
of the SMBus. SMBus is built upon I
2
C with some minor
differences in timing, DC parameters and protocol. The
SMBus protocols are more robust than simple I
2
C byte
commands because they provide timeouts to prevent
bus hangs and optional Packet Error Checking (PEC) to
ensure data integrity. In general, a master device that
can be configured for I
2
C communication can be used
for PMBus communication with little or no change to
hardware or firmware.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification Part
1 Revision 1.1: Section 5: Transport. This can be found at:
www.pmbus.org
For a description of the differences between SMBus and I
2
C,
refer to System Management Bus (SMBus) Specification
Version 2.0: Appendix B – Differences between SMBus
and I
2
C. This can be found at:
www.smbus.org
When using an I
2
C controller to communicate with a PMBus
part it is important that the controller be able to write a
byte of data without generating a stop. This will allow the
controller to properly form the repeated start of a PMBus
read command by concatenating a start command byte
write with an I
2
C read.
Device Address
The I
2
C/SMBus address of the LTC2974 equals the base
address + N where N is a number from 0 to 8. N can be
configured by setting the ASEL0 and ASEL1 pins to V
DD33
,
GND or FLOAT. See Table 1. Using one base address and
the nine values of N, nine LTC2974s can be connected
together to control thirty six outputs. The base address is
stored in the MFR_I2C_BASE_ADDRESS register. The base
address can be written to any value, but generally should
not be changed unless the desired range of addresses
overlap existing addresses. Watch that the address range
does not overlap with other I
2
C/SMBus device or global
addresses, including I
2
C/SMBus multiplexers and bus
buffers. This will bring you great happiness.