Datasheet

LTC2970/LTC2970-1
6
29701fc
29701 TD
SDA
SCL
START
CONDITION
t
BUF
t
r
t
SU;STO
STOP
CONDITION
t
HD;STA
t
SU;DAT
t
SU;STA
REPEATED START
CONDITION
t
HIGH
t
HD;DAT
t
SP
t
HD;STA
t
LOW
t
f
t
f
START
CONDITION
t
r
The I
2
C Bus Specifi cation
Note 4: Integral nonlinearity (INL) is defi ned as the deviation of a code
from a straight line passing through the actual endpoints (0V and 6V)
of the transfer curve. The deviation is measured from the center of the
quantization band.
Note 5: Nonlinearity is defi ned from the fi rst code that is greater than or
equal to the maximum offset specifi cation to code 255 (full-scale).
Note 6: Maximum capacitive load, C
B
, for SCL and SDA is 400pF. Data and
clock risetime (t
r
) and falltime (t
f
) are: (20 + 0.1 • C
B
)(ns) < t
r
< 300ns and
(20 + 0.1 • C
B
)(ns) < t
f
< 300ns. C
B
= capacitance of one bus line in pF.
SCL and SDA external pull-up voltage, V
IO
, is 3V < V
IO
< 5.5V.
Note 7: This specifi cation is guaranteed by design.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specifi ed.
Note 3: TUE (%) is defi ned as:
%
(• / )
•Gain Error
INL V LSB V
V
OS
IN
+
+500
100
μ
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
SETUP_TRACK
Tracking IDAC Disconnect Delay LTC2970-1 Only: After the tracking
algorithm asserts CPIO_CFG high, the
LTC2970-1 will wait this amount of time
before starting to decrement Chn_a_
delay_track[9:0]. Used while tracking
power supplies off.
32 ms
t
DEC_TRACK
Tracking IDAC Decrement Rate LTC2970-1 Only: The LTC2970-1 changes
Chn_a_delay_track[9:0] at this rate.
88 μs/LSB
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C.
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAM