Datasheet

LTC2970/LTC2970-1
27
29701fc
APPLICATIO S I FOR ATIO
WUU
U
OPERATIO
U
Rules:
See “Generating and Monitoring Instantaneous Faults”.
18. General Purpose Input/Output Pins
The GPIO_0 and GPIO_1 may be used to: (1) monitor
instantaneous faults (see “Generating and Monitoring
Instantaneous faults”); (2) control switcher run/start pins
during tracking (see “Tracking Power Supplies Overview”);
or (3) provide general purpose input/output pins.
Procedure:
To program GPIO_n as an open drain output set Io_cfg_n
= 2’b10. The value written to lo_gpio_n will be output
over GPIO_n.
To program GPIO_n as an input set Io_cfg_n = 2’b11. The
value of GPIO_n may now be read through lo_gpio_n.
Rules:
The power on reset confi gurations for GPIO_0 and GPIO_1
are output pins with a value equal to the complement of
the GPIO_CFG level.
19. Advanced Development Features
The internal ADC may be disabled with the ADC result
registers accepting written I
2
C data. This feature allows
faults to be generated for diagnostic purposes, without
having to generate an actual overvoltage or undervoltage
event.
Procedure:
Set IO(Io_i2c_adc_wen) high to enable ADC result register
writes and disable internal ADC updates.
Rules:
Io_i2c_adc_wen must be clear for normal operation.
Margining DC/DC Converters with External Feedback
Resistors
Figure 1 shows a typical application circuit for margining
a power supply with an external feedback network. The
V
IN0_AP
and V
IN0_AM
differential inputs sense the load volt-
age directly, and differential inputs V
IN0_BP
and V
IN0_BM
are connected across load current sense resistor R50. A
correction voltage is developed at the I
OUT0
pin by sourcing
IDAC0’s current into resistor R40. R40 is Kelvin connected
to the point-of-load GND in order to isolate V
IOUT0
from
ground bounce due to load current changes. V
IOUT0
is
replicated at V
OUT0
by an on-chip, unity-gain voltage buffer.
V
OUT0
is then connected to the feedback node of the power
supply through resistor R30. The feedback node can be
isolated from the DAC’s correction voltage by placing the
V
OUT0
pin in high-impedance mode. Since the GPIO_CFG
pin is pulled-up to V
DD
, the LTC2970’s GPIO_0 pin will
automatically hold the power supply’s RUN/SS pin low
after power-up until the I
2
C interface releases it.
Figure 1. Typical LTC2970 Application Circuit for
DC/DC Converters with External Feedback Resistors
OUT
FB
R40R10
R20
R30
R50
0.1μF
0.1μF
I
–
I
+
1/2 LTC2970
V
IN0_BM
V
IN0_BP
V
IN0_AP
V
DC0
+
–
V
OUT0
I
OUT0
V
IN0_AM
ALERT
SCL I
2
C BUS
SDA
GPIO_0
REF
V
IN
GND
GND
ASEL0
ASEL1
LOAD
V
DD
GPIO_CFG
DC/DC
CONVERTER
SGND
29701 F01
RUN/SS
IN
V
IN
8V TO 15V
0.1μF