Datasheet

LTC2970/LTC2970-1
25
29701fc
OPERATIO
U
Table 7. LTC2970 ADC Conversion and Fault Limit Registers
INPUT CHANNEL ADC_MON()
CONTROL BIT
ADC RESULT REGISTER
(2s COMPLEMENT)
OV FAULT REGISTER
(2s COMPLEMENT)
UV FAULT REGISTER
(2s COMPLEMENT)
TEMPERATURE Adc_mon_temp Temp_adc[14:0] - -
VIN1_BP-VIN1_BM Adc_mon_b_ch1 Ch1_b_adc[14:0] Ch1_b_ov[14:0] Ch1_b_uv[14:0]
VIN1_AP-VIN1_AM Adc_mon_a_ch1 Ch1_a_adc[14:0] Ch1_a_ov[14:0] Ch1_a_uv[14:0]
VIN0_BP-VIN0_BM Adc_mon_b_ch0 Ch0_b_adc[14:0] Ch0_b_ov[14:0] Ch0_b_uv[14:0]
VIN0_AP-VIN0_AM Adc_mon_a_ch0 Ch0_a_adc[14:0] Ch0_a_ov[14:0] Ch0_a_uv[14:0]
12VIN Adc_mon_v12 V12_adc[14:0] V12_ov[14:0] V12_uv[14:0]
VDD Adc_mon_vdd Vdd_adc[14:0] Vdd_ov[14:0] Vdd_uv[14:0]
reset each time the result register is read. This provides a
simple mechanism for supervisory software to determine
if a new conversion has been completed since data was
last read.
Rules:
The LTC2970 assigns priority to ADC conversions of
CH1_A_ADC and CH0_A_ADC when these channels are
in their initial fast servo mode.
The IO() register control bit Io_i2c_adc_wen must be low
in order for ADC conversions to be performed.
LTC2970-1 Only: ADC conversions are suspended during
any pending tracking requests.
16. Generating and Monitoring Instantaneous Faults
The LTC2970 supports fourteen different types of instan-
taneous faults. These faults together with the conditions
that trigger them are defi ned in Table 8. There are six
under-voltage faults, six over-voltage faults and two IDAC
limit faults. The FAULT() command may be used to read
the status of all instantaneous fault bits. The IO() com-
mand may be used to confi gure GPIO_0 and GPIO_1 to
view voltage limit and IDAC faults respectively. The state
of GPIO_0 and GPIO_1 may be read using IO().
Table 8. LTC2970 Fault Reporting Bits and Conditions
CONDITION THAT GENERATES AN
INSTANTANEOUS FAULT
FAULT()
INSTANTANEOUS FAULT REPORTING
FAULT_EN()
ENABLE FOR LATCHED FAULT REPORTING
FAULT_LA()
LATCHED FAULT REPORTING
V12_adc[14:0] < V12_uv[14:0] Fault_v12_uv Fault_en_v12_uv Fault_la_v12_uv
V12_adc[14:0] > V12_ov[14:0] Fault_v12_ov Fault_en_v12_ov Fault_la_v12_ov
Vdd_adc[14:0] < Vdd_uv[14:0] Fault_vdd_uv Fault_en_vdd_uv Fault_la_vdd_uv
Vdd_adc[14:0] > Vdd_ov[14:0] Fault_vdd_ov Fault_en_vdd_ov Fault_la_vdd_ov
Ch1_b_adc[14:0] < Ch1_b_uv[14:0] Fault_ch1_b_uv Fault_en_ch1_b_uv Fault_la_ch1_b_uv
Ch1_b_adc[14:0] > Ch1_b_ov[14:0] Fault_ch1_b_ov Fault_en_ch1_b_ov Fault_la_ch1_b_ov
Idac_a_ch1[7:0] = 8’ff or 8’h00 Fault_ch1_a_idac Fault_en_ch1_a_idac Fault_la_ch1_a_idac
Ch1_a_adc[14:0] < Ch1_a_uv[14:0] Fault_ch1_a_uv Fault_en_ch1_a_uv Fault_la_ch1_a_uv
Ch1_a_adc[14:0] > Ch1_a_ov[14:0] Fault_ch1_a_ov Fault_en_ch1_a_ov Fault_la_ch1_a_ov
Ch0_b_adc[14:0] < Ch0_b_uv[14:0] Fault_ch0_b_uv Fault_en_ch0_b_uv Fault_la_ch0_b_uv
Ch0_b_adc[14:0] > Ch0_b_ov[14:0] Fault_ch0_b_ov Fault_en_ch0_b_ov Fault_la_ch0_b_ov
Idac_a_ch0[7:0] = 8’ff or 8’h00 Fault_ch0_a_idac Fault_en_ch0_a_idac Fault_la_ch0_a_idac
Ch0_a_adc[14:0] < Ch0_a_uv[14:0] Fault_ch0_a_uv Fault_en_ch0_a_uv Fault_la_ch0_a_uv
Ch0_a_adc[14:0] > Ch0_a_ov[14:0] Fault_ch0_a_ov Fault_en_ch0_a_ov Fault_la_ch0_a_ov