Datasheet

LTC2953
7
2953f
PIN FUNCTIONS
GND (Pin 1): Ground.
VM (Pin 2): Voltage Monitor Input. Input to an accurate
comparator with a 0.5V threshold. VM controls the state
of the
R
S
T output pin and is independent of
P
B,
P
F
I and
UVLO status. A voltage below 0.5V on this pin asserts
R
S
T low. Connect to GND if unused.
K
I
L
L (Pin 3):
K
I
L
L Input. Forcing
K
I
L
L low releases the
enable output. During system turn on, this pin is blanked
by a 512ms internal timer (t
KILL, ON BLANK
) to allow the
system to pull
K
I
L
L high. This pin has an accurate 0.6V
threshold and can be used as a power kill voltage monitor.
Set the pin voltage above its threshold if unused.
PDT (Pin 4): Power Down Time Input. A capacitor to
ground determines the additional time (6.4 seconds/μF)
that
P
B or UVLO must be held low before releasing the
EN/
E
N and
I
N
T outputs. If this pin is left open, the power
down delay time defaults to 64ms.
P
B (Pin 5): Push Button Input. Connecting
P
B to ground
through a momentary switch provides On/Off control via the
EN/
E
N and
I
N
T outputs. An internal 100k pull-up resistor
connects to an internal 1.9V bias voltage. The rugged
P
B
input withstands ±10kV ESD HBM and can be pulled up to
27V externally without consuming extra current. Voltages
below ground will not damage the pin.
V
IN
(Pin 6): Power Supply Input: 2.7V to 27V.
UVLO (Pin 7): UVLO Comparator Input. When UVLO drops
below its falling threshold (0.5V) for more than 32ms, the
LTC2953 asserts
I
N
T low, thereby requesting a system
power down. If UVLO remains below its falling threshold
(0.5V) for longer than the adjustable power down delay,
the enable output is released. Additionally, UVLO provides
a
P
B lock out feature that prevents the user from asserting
the enable output when UVLO falls below its threshold.
Connect to V
IN
if unused.
PFI (Pin 8): Power Fail Comparator Input. Input to an ac-
curate comparator with a 0.5V falling threshold and 4mV
of hysteresis. PFI controls the state of the
P
F
O output pin
and is independent of
P
B, VM and UVLO status. Connect
to GND if unused.
P
F
O (Pin 9): Power Fail Output. This pin is a high voltage
open drain pull-down.
P
F
O pulls low when PFI is below
0.5V. Open circuit when unused.
R
S
T (Pin 10): Reset Output. This pin is an open drain
pull-down. Pulls low when VM input is below 0.5V and is
held low for 200ms after VM input is above 0.5V. Open
circuit when unused.
EN (LTC2953-1, Pin 11): Open Drain Enable Output. This
output is intended to enable system power. EN is asserted
high after a valid
P
B turn on event (t
DB, ON
). EN is released
low if: a)
K
I
L
L is not driven high (by μP) within 512ms of
the initial valid
P
B power turn on event, b)
K
I
L
L is driven
low during normal operation, c)
P
B or UVLO is asserted and
held low (t > t
PD, Min
+ t
PDT
) during normal operation.
E
N (LTC2953-2, Pin 11): Open Drain Enable Output. This
output is intended to enable system power.
E
N is asserted
low after a valid
P
B turn on event (t
DB, ON
).
E
N is released
high if: a)
K
I
L
L is not driven high (by μP) within 512ms of
the initial valid
P
B power turn-on event, b)
K
I
L
L is driven
low during normal operation, c)
P
B or UVLO is asserted and
held low (t > t
PD, Min
+ t
PDT
) during normal operation.
I
N
T (Pin 12): Open Drain Interrupt Output. After a turn off
event is detected (t
DB, OFF
) from
P
B or UVLO, the LTC2953
interrupts the system (μP) by asserting
I
N
T low. The μP
would perform power down and housekeeping tasks and
then assert the
K
I
L
L pin low, thus releasing the enable out-
put. The
I
N
T pulse width is a minimum of 32ms and stays
low as long as
P
B is asserted. If
P
B is asserted for longer
than t
PD, Min
+ t
PDT
, however, the
I
N
T and EN/
E
N outputs
are immediately released. Open circuit when unused.
Exposed Pad (Pin 13): Exposed Pad may be left open or
connected to ground.