Datasheet

LTC2953
14
2953f
APPLICATIONS INFORMATION
Aborted Power On Sequence
The LTC2953 provides an internal 512ms timer to detect
when a system fails to power on properly. A power on
sequence begins by debouncing the
⎯
P
⎯
B input. After the
enable pin is subsequently asserted, the LTC2953 starts
the 512ms blanking timer (t
KILL, ON BLANK
). If the
⎯
K
⎯
I
⎯
L
⎯
L
input is not driven high within this 512ms time window,
the enable pin is immediately released, thus turning off
system power. This failsafe feature prevents a user from
turning on the device when the circuits driving the
⎯
K
⎯
I
⎯
L
⎯
L
input do not respond within 512ms after enable has been
asserted. See Figure 12.
μP Turns Off System Power During Normal Operation
Once the system has powered on and is operating normally,
the μP can turn off power by asserting the
⎯
K
⎯
I
⎯
L
⎯
L input low.
See Figure 13.
DUAL FUNCTION BATTERY SUPERVISOR
The LTC2953 provides two comparators for battery
monitoring: an uncommitted power fail comparator and
a latched low battery comparator with μP interrupt. The
application shown in Figure 14 monitors a 2 cell Li-Ion
battery stack.
Power Fail Comparator
This comparator provides real time threshold information
and can serve as the fi rst warning of a decaying battery or
supply. The
⎯
P
⎯
F
⎯
O output is driven low when the PFI input
voltage drops below its falling threshold (0.5V) and is
high impedance when PFI rises above its rising threshold
(0.504V). The low leakage, high voltage PFI input (10nA,
maximum) allows the use of large valued external resistors,
which lowers system current consumption.
UVLO Comparator
The under voltage lockout comparator performs three
functions: a) interrupts the μP when a supply glitch drives
the UVLO voltage below its falling threshold (0.5V) for
longer than 32ms, followed by b) forces system power
off when the UVLO voltage falls below its falling threshold
(0.5V) for t
PD, Min
+ t
PDT
, c) locks out the enable (prevents
system power on) output if UVLO voltage is below its fall-
ing threshold (0.5V) during system power on. See Figures
15A and 15B.
The low leakage (10nA, maximum), high voltage UVLO
input allows the use of large valued external resistors.
See Figure 14.
t
DB, ON
t
KILL, ON BLANK
PB
KILL
EN
(LTC2953-1)
2953 F12
PB, UVLO AND KILL
IGNORED
SYSTEM FAILS TO SET KILL HIGH
TURN ON ABORTED
t
KILL(PD)
KILL
EN
(LTC2953-1)
2953 F13
SYSTEM SETS KILL LOW
SYSTEM POWER OFF
Figure 12. Aborted Power On Sequence,
⎯
K
⎯
I
⎯
L
⎯
L
Remaining Low Aborts Power On Sequence
Figure 13. μP Turns Off System Power