Datasheet

LTC2952
19
2952fb
Figure 9. Setting the Comparator Trip Point
0.5V
PIN
V
TRIP
2952 F09
–
+
+
–
R2
1%
R1
1%
APPLICATIONS INFORMATION
Accurate Comparator Input Pins
VM, PFI, KILL, M1 and M2
VM, PFI, KILL, M1 and M2 are high impedance input pins
to accurate comparators with a falling threshold of 0.500V.
Note the following differences between some of these pins:
the VM pin comparator has no hysteresis while the other
comparators have 15mV hysteresis and the M1 pin has a
3μA pull-up current while the other input pins do not.
Figure 9 shows the configuration of a typical application
when VM, PFI, KILL or M2 pin connects to a tap point on
an external resistive divider between a positive voltage
and ground.
Calculate the falling trip voltage from the resistor divider
value using:
V
FALLING−TRIP
= 0.5V 1+
R1
R2
⎛
⎝
⎜
⎞
⎠
⎟
Table 1 shows suggested 1% resistor values for various
applications.
Table 1. Suggested 1% Resistor Values for the Accurate
Comparators (–6.5% Nominal Threshold)
V
SUPPLY
(V)
V
TRIP
(V)
R1
(kΩ)
R2
(kΩ)
12 11.25 2150 100
10 9.4 1780 100
8 7.5 1400 100
7.5 7 1300 100
6 5.6 1020 100
5 4.725 845 100
3.3 3.055 511 100
3 2.82 464 100
2.5 2.325 365 100
1.8 1.685 237 100
1.5 1.410 182 100
1.2 1.120 124 100
1.0 0.933 86.6 100
0.9 0.840 68.1 100
0.8 0.750 49.9 100
0.7 0.655 30.9 100
0.6 0.561 12.1 100
In a typical application the M1 pin is usually either
connected to ground or left floating. When left floating,
the internal 3μA pull-up drives the M1 pin high above
its rising threshold (0.515V). Note that this 3μA pull-up
current can be used to pull up any or all of the other high
impedance input pins. For example, connect the M2 pin to
the M1 pin to pull both up above their rising thresholds,
as shown in Figure 5.
The Voltage Monitor and Watchdog Function
The first voltage monitor input is PFI. As mentioned
before, this pin is a high impedance input to an accurate
comparator with 15mV hysteresis. When the voltage at
PFI is higher than its rising threshold (0.515V), the PFO
pin is high impedance. Conversely, when the voltage level
at PFI is lower than its falling threshold (0.500V), the PFO
pin strongly pulls down to GND.
The second voltage monitor input is VM. The VM pin
together with the WDE pin (acting as a watchdog monitor
pin) affects the state of the RST output pin. The VM pin is
also a high impedance input to an accurate comparator.
However, the VM comparator has no hysteresis and hence
the same rising and falling threshold (0.500V).
When the voltage level at VM is less than 0.5V, the RST pin
strongly pulls down to GND. When the voltage level at VM
first rises above 0.5V, the RST output pin is held low for
another 200ms (t
RST
) before turning high impedance.
After the RST pin becomes high impedance, if the WDE
input pin is not left in a Hi-Z state, the watchdog timer
is started. The watchdog timer is reset every time there
is an edge (high to low or low to high transition) on the