Datasheet

LTC2942
14
2942fa
applicaTions inFormaTion
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address 1100100 and the
R/W bit set to zero, as shown in Figure 6. The LTC2942
acknowledges and then the master sends a command
byte which indicates which internal register the master is
to read. The LTC2942 acknowledges and then latches the
command byte into its internal register address pointer. The
master then sends a repeated START condition followed
by the same seven bit address with the R/W bit now set
to one. The LTC2942 acknowledges and sends the con-
tents of the requested register. The transmission is ended
when the master sends a STOP condition. If the master
acknowledges the transmitted data byte, the LTC2942
increments its address pointer and sends the contents of
the following register as depicted in Figure 7.
Alert Response Protocol
In a system where several slaves share a common inter-
rupt line, the master can use the alert response address
(ARA) to determine which device initiated the interrupt
(Figure 8).
S R
ALERT RESPONSE ADDRESS DEVICE ADDRESS
2942 F08
A
1
0001100 11001001
0 1
P
A
Figure 8. LTC2942 Serial Bus SDA Alert Response Protocol
S10ms W
ADDRESS REGISTER S
2942 F09
A A ADDRESS
0
1100100 08h 1
0 0 1100100
0
P
R
0
A
F1h
DATA
80h
DATA
A
1
A
S W
ADDRESS REGISTER DATA
A A
0
1100100 01h BC
0 0
P
Figure 9. Voltage Conversion Sequence
S W
ADDRESS REGISTER S
2942 F10
A A ADDRESS
0
1100100 02h 1
0 0 1100100
0
P
R
0
A
80h
DATA
01h
DATA
A
1
A
Figure 10. Reading the LTC2942 Accumulated Charge Registers (C, D)
S W
ADDRESS REGISTER S
2942 F06
A A ADDRESS
0
1100100 00h 1
0 0 1100100
0
P
R
1
A
01h
DATA
A
Figure 6. Reading the LTC2942 Status Register (A)
S W
ADDRESS REGISTER S
2942 F07
A A ADDRESS
0
1100100 08h 1
0 0 1100100
0
P
R
0
A
F1h
DATA
24h
DATA
A
1
A
Figure 7. Reading the LTC2942 Voltage Register (I, J)