Datasheet

LTC2941
12
2941fa
applicaTions inFormaTion
Alert Response Protocol
In a system where several slaves share a common interrupt
line, the master can use the alert response address (ARA)
to determine which device initiated the interrupt (Figure 9).
FROM MASTER TO SLAVE
S W
ADDRESS REGISTER DATA
FROM SLAVE TO MASTER
2941 F05
A: ACKNOWLEDGE (LOW)
A: NOT-ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
A A A
0
1100100 01h FCh
0 0 0
P
Figure 5. Writing FCh to LTC2941 Control Register (B)
S W
ADDRESS REGISTER DATA
2941 F06
A A A
0
1100100 02h F0h 01h
0 0 0
0
P
DATA
A
Figure 6. Writing F001h to the LTC2941 Accumulated Charge Registers (C, D)
S W
ADDRESS REGISTER S
2941 F07
A A ADDRESS
0
1100100 00h 1
0 0 1100100
0
P
R
1
A
81h
DATA
A
Figure 7. Reading the LTC2941 Status Register (A)
S W
ADDRESS REGISTER S
2941 F08
A A ADDRESS
0
1100100 02h 1
0 0 1100100
0
P
R
0
A
80h
DATA
01h
DATA
A
1
A
Figure 8. Reading the LTC2941 Accumulated Charge Registers (C, D)
S R
ALERT RESPONSE ADDRESS DEVICE ADDRESS
2941 F09
A
1
0001100 11001001
0 1
P
A
Figure 9. LTC2941 Serial Bus SDA Alert Response Protocol
The master initiates the ARA procedure with a START con-
dition and the special 7-bit ARA bus address (0001100)
followed by the read bit (R) = 1. If the LTC2941 is asserting
the AL/CC pin in alert mode, it acknowledges and responds
by sending its 7-bit bus address (1100100) and a 1. While