Datasheet

LTC2938/LTC2939
14
293839ff
APPLICATIONS INFORMATION
After RST returns high, the microprocessor can poll the
state of the WDO pin to determine if the reset was caused
by an undervoltage condition or by a watchdog timeout.
WDO high means that the reset was caused by undervolt-
age since this condition also resets the WDO latch (and
the watchdog timer). If the WDO pin is low, the system
reset was caused by watchdog timeout. The microproces-
sor can then change the state of WDI to clear the WDO
latch. If the microprocessor fails to do so, the LTC2938/
LTC2939 will alternate between t
RST
and t
WD
timeout
and RST will be pulled low for t
RST
after every watchdog
timeout. WDO remains low until the microprocessor fl ips
the state of WDI.
Some microprocessors force their I/O pins into high
impedance during reset which in turn, fl oats the WDI
pin. This affects the response of the LTC2938/LTC2939.
When the WDI pin is fl oated, the watchdog timer is reset
and C
WT
is discharged towards ground but WDO remains
unchanged. Putting WDI in high impedance does not affect
t
RST
. Once RST goes high again, and WDI is driven from
high impedence to a high or low state, the watchdog timer
starts a complete t
WD
timeout period. A high-to-low or
low-to-high transition at WDI clears WDO if it was previ-
ously latched low.
The RST and WDO pins should not be tied together to
generate the master reset signal since a watchdog timeout
forces RST low together with WDO and the master reset
signal will remain low indefi nitely.
Figure 5. 6-Supply Monitor, 12V (ADJ), 5V, 3.3V, 2.5V, 1.8V, 1.2V (ADJ)
with Watchdog Enabled
V
REF
LTC2939
293839 F05
2150k 1%
R1
59k
1%
5V
0.1μF
3.3V
2.5V
1.8V
12V
100k
1%
R2
40.2k
1%
100k
1%
C
RT
47nF
C
WT
47nF
t
RST
= 94ms
t
WD
= 940ms
0.1μF
WDI
WDO
RST
V
PG
GND CRT CWT
V1
V2
V3
V4
V5
V6
124k 1%
1.2V
MICROPROCESSOR